Job Summary

This role is responsible for contributing to the design and implementation of standard cell circuits within semiconductor design projects. The position focuses on applying foundational knowledge of STD-cell circuit design methods to develop, test, and maintain digital circuit blocks, ensuring deliverables meet defined quality and performance standards.

Key Responsibilities

1. Apply basic understanding of STD-cell circuit design using industry-standard EDA tools such as Cadence Virtuoso and Synopsys Custom Compiler to implement digital logic cells as per project specifications.
2. Develop and validate circuit layouts by utilizing foundational knowledge of transistor-level design and simulation tools such as Spectre, ensuring compliance with design rules and performance metrics.
3. Participate in debugging and troubleshooting of existing standard cell library elements using layout verification tools like Calibre for DRC/LVS checks.
4. Document design process steps and maintain records of circuit modifications using project tracking platforms and collaborative documentation tools.
5. Collaborate within the team to understand feature requirements and assist in the development of circuit blocks that align with client needs.

Skill Requirements

1. Basic understanding of STD-cell circuit design fundamentals and digital logic implementation.
2. Familiarity with EDA tools including Cadence Virtuoso, Synopsys Custom Compiler, and layout verification tools such as Calibre.
3. Fundamental knowledge of transistor-level design and simulation principles.
4. Ability to maintain clear documentation of design activities and results.

Other Requirements

1. Optional: Cadence Certified Custom IC Design Specialist (Foundational Level)
2. Optional: Synopsys Custom Design Certification (Entry Level)