AI Solution Architect II
United States
Job Description
AI Solution Architect II
New York, New York

Job Summary

This role focuses on supporting and enhancing standard cell circuit design activities within the semiconductor development process. The individual is responsible for maintaining, troubleshooting, and improving existing circuit features and delivering quality solutions for assigned tasks. They contribute to technical documentation and assist in gathering requirements, ensuring timely and accurate outputs in line with project objectives.

Key Responsibilities

1. Maintain and update standard cell libraries using EDA tools such as Cadence Virtuoso, ensuring compliance with process technology specifications and resolving functionality issues.
2. Troubleshoot and debug circuit-level challenges in STD-cell designs using simulation tools like Spectre and HSPICE, supporting enhancement and bug-fix requests.
3. Support enhancement and minor feature development by implementing design modifications through schematic and layout editing in accordance with client or team requirements.
4. Participate in peer code and schematic reviews, providing technical inputs based on foundational knowledge of CMOS circuit design and design-for-manufacturability.
5. Prepare and update technical documentation, including design specifications and test reports, to facilitate CMMi compliance and meet client deliverable standards.
6. Collaborate within the design team to collect requirements and clarify technical queries related to standard cell development and validation.

Skill Requirements

1. Strong understanding of STD-Cell circuit design fundamentals, including CMOS logic gates and standard cell architectures.
2. Experience with EDA tools such as Cadence Virtuoso, Spectre, and HSPICE for schematic capture, simulation, and layout editing.
3. Good familiarity with semiconductor process technologies and design rules.
4. Ability to prepare technical documentation and specifications for design flows.
5. Experience in troubleshooting circuit performance issues using simulation and debug tools.

Other Requirements

1. Optional but valuable: Cadence Certified Design Engineer (CCDE) or equivalent EDA certification.
Maximum Salary (US):  290000
Minimum Salary (US):  240000
Information at a Glance

Why HCLTech?

At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first.

HCLTech is a global technology company, home to more than 226,300 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending December 2025 totaled $14.5 billion.

Compensation and Benefits

A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year.