Job Summary
| Candidates with 5 to 7 years experience is mandatory |
| Experience in Full chip RTL integration is preferred |
| Experience with ASIC/SoC development flow including synthesis/timing constraints development, Static Timing Analysis closure, resolving P& R congestion issues etc. |
| Experience in RTL Synthesis |
| Scripting experience |
| Experience integrating IP's like PCIe, USB, Ethernet etc. |
| Should be able to lead a team of 2 to 3 Entry Level engineers |
Key Responsibilities
2. Lead A Team Of Rtl Designers, Providing Mentorship And Guidance To Ensure The Delivery Of High-Quality Design Solutions That Meet Industry Standards And Business Requirements.
3. Present Rtl Design Concepts And Strategies To Stakeholders, Facilitate Discussions, And Incorporate Feedback To Refine And Enhance Design Outcomes.
4. Establish And Maintain Design Standards, Guidelines, And Best Practices Specific To Rtl Design, Promoting A Consistent And High-Quality Design Approach Across Projects.
5. Stay Updated On Industry Trends And Emerging Technologies Relevant To Rtl Design, Driving Innovation And Excellence In Design Practices And Solutions.
Skill Requirements
2. Strong Understanding Of Design Standards And Best Practices Specific To Rtl Design.
3. Proficient In Using Design Tools And Technologies Relevant To Rtl Design.
4. Excellent Communication And Leadership Skills For Effective Team And Stakeholder Collaboration.
5. Ability To Integrate Business Objectives Into Design Strategies.