Job Summary

Role OverviewWe are looking for a Simulation Engineer to develop and execute pre-silicon simulation-based verification for complex SoC and subsystem designs. The role involves feature validation, performance correlation, security verification, and coverage closure across multiple IP and SoC domains.

Key Responsibilities

Develop and execute simulation-based verification plans.Validate features across:Performance (KPI validation and correlation)Security (Trusted P2P, Secure ATS, HAC)MIO, VTD, and debug support flowsRAS functionality and SoC coverageMCP_SIM execution environmentsDrive feature validation, regression execution, and debug.Perform simulation-based performance characterization and KPI correlation.Track and improve functional and code coverage metrics.Work with architects and designers to resolve specification and RTL issues.Contribute to automation, testbench enhancements, and verification infrastructure.

Skill Requirements

Strong background in SystemVerilog and UVM.Experience in SoC verification and simulation-based validation.Understanding of PCIe, CXL, memory hierarchy, coherency, virtualization, and security concepts.Experience with regression management and coverage closure.Strong scripting skills in Python, Perl, or Shell.Excellent debugging and analytical skills.

Other Requirements

4-12 years of Design Verification or Simulation experience.Performance validation experience is preferred but not mandatory.Education (Both Roles)B.E./B.Tech/M.E./M.Tech in Computer Engineering, Electronics, Electrical Engineering, or related field.