Job Summary

This role is responsible for architecting, designing, and delivering memory layout solutions within hardware and embedded systems projects. The individual serves as a subject matter expert, driving technical excellence and innovation by leveraging advanced memory mapping strategies and tools. They ensure project outcomes meet stringent quality standards and client requirements while fostering knowledge growth and technical leadership within the team.

Key Responsibilities

1. Architect and design advanced memory layouts using industry-standard tools such as Synopsys Memory Compiler and Cadence Virtuoso, ensuring optimal performance and reliability in silicon and embedded solutions.
2. Lead solution development for product and sustenance projects by applying expert knowledge in SRAM, DRAM, and Flash memory organization, guiding team members through implementation phases.
3. Provide subject matter expertise in memory mapping, address decoding, and timing closure, supporting complex problem-solving and technical escalations.
4. Evaluate project deliverables by reviewing schematic and layout designs for memory blocks using EDA tools, ensuring compliance with quality metrics and best practices.
5. Drive adoption of new memory technologies and methodologies, including non-volatile memory layouts and low-power design techniques, to maintain solution relevance and quality.
6. Mentor and train team members in memory layout concepts, EDA tool usage, and verification flows to strengthen team capability and mitigate delivery risks.
7. Collaborate with stakeholders to gather specifications and translate requirements into robust memory architecture solutions aligned with client domains and technology needs.
8. Recommend and implement value creation initiatives by benchmarking memory layout approaches, integrating industry best practices, and optimizing for performance and area efficiency.

Skill Requirements

1. Expert proficiency in memory layout design using Synopsys, Cadence, or Mentor Graphics EDA tools.
2. Excellent understanding of memory organization principles for SRAM, DRAM, Flash, and non-volatile memories.
3. Advanced skills in memory mapping, address decoding, and timing closure techniques.
4. Solid capability in schematic capture, layout editing, and physical verification for memory blocks.
5. Strong knowledge of low-power memory design and reliability optimization.
6. Experience with memory verification flows, DRC/LVS checks, and post-layout simulation.

Other Requirements

1. Certified Cadence Virtuoso Layout Designer (optional but valuable)
2. Synopsys Certified Memory Designer (optional but valuable)