Group Technical Architect - Silicon Platform Validation, Python
India
Job Description
Group Technical Architect - Silicon Platform Validation, Python
Bengaluru, Karnataka
Job Summary
This role leads advanced RTL design initiatives, driving technical excellence in digital circuit architecture and implementation. The individual provides subject matter expertise, mentors team members, and champions industry-leading methodologies to deliver high-quality, future-ready solutions that align with organizational and client objectives.
Key Responsibilities
1. Architect complex digital systems by defining and optimizing RTL structures using Verilog/VHDL, ensuring robust functionality and performance.
2. Guide the team in developing and verifying RTL modules with industry-standard EDA tools such as Synopsys Design Compiler and Cadence Genus, promoting best-in-class coding practices.
3. Mentor engineers on advanced RTL design concepts, conducting technical training and facilitating knowledge transfer on evolving semiconductor technologies.
4. Analyze project specifications and translate client requirements into efficient RTL solutions, leveraging domain expertise to address functional and timing constraints.
5. Serve as a technical authority by reviewing and enhancing RTL implementation strategies, supporting issue resolution and design closure.
6. Drive competency development through authoring whitepapers, conducting market trend analysis, and developing collateral that articulates innovative design approaches.
7. Recommend and implement value-added initiatives by integrating industry best practices and emerging methodologies in RTL design, maximizing client outcomes and project success.
2. Guide the team in developing and verifying RTL modules with industry-standard EDA tools such as Synopsys Design Compiler and Cadence Genus, promoting best-in-class coding practices.
3. Mentor engineers on advanced RTL design concepts, conducting technical training and facilitating knowledge transfer on evolving semiconductor technologies.
4. Analyze project specifications and translate client requirements into efficient RTL solutions, leveraging domain expertise to address functional and timing constraints.
5. Serve as a technical authority by reviewing and enhancing RTL implementation strategies, supporting issue resolution and design closure.
6. Drive competency development through authoring whitepapers, conducting market trend analysis, and developing collateral that articulates innovative design approaches.
7. Recommend and implement value-added initiatives by integrating industry best practices and emerging methodologies in RTL design, maximizing client outcomes and project success.
Skill Requirements
1. Expert proficiency in RTL design using Verilog and VHDL.
2. Excellent command of synthesis, timing analysis, and logic optimization with EDA tools (Synopsys, Cadence, Mentor Graphics).
3. In-depth understanding of digital circuit architecture, FPGA/ASIC flows, and design for testability.
4. Advanced skills in protocol implementation, clock domain crossing, and low-power design techniques.
5. Expert ability to articulate technical concepts, mentor teams, and drive strategic technical decisions.
2. Excellent command of synthesis, timing analysis, and logic optimization with EDA tools (Synopsys, Cadence, Mentor Graphics).
3. In-depth understanding of digital circuit architecture, FPGA/ASIC flows, and design for testability.
4. Advanced skills in protocol implementation, clock domain crossing, and low-power design techniques.
5. Expert ability to articulate technical concepts, mentor teams, and drive strategic technical decisions.
Other Requirements
1. Recommended certifications:
2. IEEE Certified Professional in VLSI Design (optional but valuable)
3. Synopsys Certified Design Specialist (optional but valuable)
2. IEEE Certified Professional in VLSI Design (optional but valuable)
3. Synopsys Certified Design Specialist (optional but valuable)
Information at a Glance