Job Summary
| Perform end‑to‑end physical design flow: |
| Floorplanning |
| Power planning (PG grid, IR) |
| Placement & optimization |
| CTS (Clock Tree Synthesis) |
| Routing |
| Post‑route optimization |
| Achieve timing closure across all modes and corners |
| Resolve DRC, LVS, ERC and signoff violations |
| Handle low‑power design techniques: |
| Multi‑Vt, Multi‑voltage (UPF) |
| Power gating, clock gating |
| Perform physical verification and signoff: |
| STA (Primetime) |
| SI / Crosstalk |
| IR drop & EM analysis |
| Work on advanced nodes (7nm, 5nm, 3nm or below) |
| Collaborate with: |
| RTL & Micro‑architecture teams |
| DFT & Test engineers |
| Foundry and CAD teams |
| Debug complex timing, congestion, power, and variability issues |
| Drive methodology improvements and automation (scripts/flows) |
Key Responsibilities
2. To spearhead the architecture, design, and development (through a high-performing team) of innovative solutions for product/project & sustenance delivery, ensuring alignment with strategic objectives.
3. To ensure knowledge up-gradation and work with new technologies so that the solution is current and meets quality standards and the client requirements
4. To review architecture and design deliverables and ensure solutions adhere to industry best practices ,architectural standards simultaneously establish and enforce governance /compliance measures.
5. To train and develop team so as to ensure that there is an adequate supply of trained manpower in the said technology and delivery risks are mitigated