Job Summary

This role focuses on leading the architecture, design, and development of System-on-Chip (SoC) solutions by leveraging expertise in Verilog, UVM, C, and C++. The position is accountable for conceptualizing and delivering high-quality products that align with technical standards and client requirements. The individual will drive technical innovation, mentor team members, and ensure solutions remain current with industry advancements.

Key Responsibilities

1. Architect scalable SoC solutions using Verilog and UVM, ensuring robust design methodologies and compliance with client specifications.
2. Design verification environments with UVM to validate functional correctness of SoC designs, applying advanced testbench strategies.
3. Guide development of embedded software components in C and C++ for integration and validation of SoC features.
4. Provide technical leadership in SoC design reviews, offering expert insight on optimizing RTL code and verification processes.
5. Mentor and train team members on SoC architecture, Verilog coding standards, and UVM verification techniques to strengthen technical capabilities.
6. Evaluate emerging SoC technologies and methodologies, recommending adoption to ensure solutions remain competitive and innovative.

Skill Requirements

1. Expert proficiency in SoC architecture and design, with in-depth knowledge of Verilog and UVM for digital verification.
2. Excellent understanding of C and C++ development as applied to embedded systems and SoC integration.
3. Strong familiarity with RTL design, simulation tools (e.g., Synopsys VCS, Cadence), and advanced verification methodologies.
4. Advanced proficiency in developing and reviewing testbench architectures using UVM.
5. Solid experience in mentoring technical teams and driving best practices in SoC development.

Other Requirements

1. Recommended: Certified Verification Engineer (CVE) – UVM (Optional but valuable)
2. Recommended: IEEE Certified SoC Design Professional (Optional but valuable)