Job Summary
Good understanding of ASIC/SoC life cycle
Has participated in multiple ASIC/SoC verification till tapeout stage
Experience writing ASIC/SoC testplans
Experience in ASIC/SoC Testbench definition
Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)."
Expertise & hands-on experience in OVM/UVM methodologies using SV
Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans."
Experience in developing TB components for SOC with C, SV
Experience 5 to 10 years.
Key Responsibilities
Experience in developing TB components, including functional coverage implementation and assertion coding
Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.
Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.
Experince in SOC C based tests coding & debugging"
Experience in Gate level simulation & netlist debugging
Exeprince in regression failure analayiss
Functioncal and Code Coverage closure"
Experience in Perl/Shell scripting
Bachelor's or Master's degree in Electronics & Communication Engineering (ECE),
Electrical Engineering (EE), VLSI Design, or a closely related field"
Skill Requirements
Tools: Expert proficiency with industry-leading EDA simulators, debuggers (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verd), and emulation platforms.
"Protocols:
Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE)."
Other Requirements
"Protocols:
Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE)."
Scripting: Basic comfort working in a Linux environment and using scripting languages like Python, Tcl, or Perl for automation.