Job Summary
| Perform end‑to‑end physical design flow: |
| Floorplanning |
| Power planning (PG grid, IR) |
| Placement & optimization |
| CTS (Clock Tree Synthesis) |
| Routing |
| Post‑route optimization |
| Achieve timing closure across all modes and corners |
| Resolve DRC, LVS, ERC and signoff violations |
| Handle low‑power design techniques: |
| Multi‑Vt, Multi‑voltage (UPF) |
| Power gating, clock gating |
| Perform physical verification and signoff: |
| STA (Primetime) |
| SI / Crosstalk |
| IR drop & EM analysis |
| Work on advanced nodes (7nm, 5nm, 3nm or below) |
| Collaborate with: |
| RTL & Micro‑architecture teams |
| DFT & Test engineers |
| Foundry and CAD teams |
| Debug complex timing, congestion, power, and variability issues |
| Drive methodology improvements and automation (scripts/flows) |
Key Responsibilities
2. Lead And Mentor A Team Of Designers, Providing Strategic Guidance And Oversight To Deliver High-Quality Design Solutions That Meet Organizational Business Goals.
3. Present And Articulate Design Concepts Effectively To Stakeholders, Shaping The Overall Design Vision And Strategy While Ensuring Alignment With Business Objectives.
4. Conduct Research On Industry Trends And Emerging Technologies In Physical Design To Foster Innovation And Excellence, Implementing Best Practices To Elevate Design Processes.
Skill Requirements
2. Strong Understanding Of User Experience Principles And Design Best Practices.
3. Excellent Leadership And Team Collaboration Skills.
4. In-Depth Knowledge Of Current Industry Trends And Technologies Related To Physical Design.
Other Requirements
2. Optional But Valuable: Certified User Experience Professional (Cuxp) Or Similar Certifications.