Job Summary
Experience: 5 to 10 years
Experience with Formal Equivalence Verification (FEV) tools is a must
Execute RTL ↔ Netlist, Netlist ↔ Netlist, and ECO FEV at block and full-chip levels
Debug and resolve non-equivalence failures, aborted points, and compare issues due to synthesis, ECO, scan, and DFT logic
Create and maintain reference FEV flows and testcases to validate tool features and methodologies
Develop and automate workflows to improve efficiency and runtime of FEV signoff. Automation using Python/ Perl/Tcl is preferred
Work closely with RTL, Synthesis, DFT, and Physical Design teams for issue closure.
Generate signoff-ready reports and ensure adherence to project signoff criteria
Write clear documentation for FEV flows and train users on tool usage and best practices
Key Responsibilities
Signoff & Methodology
Lead signoff STA using tools like:
Synopsys PrimeTime
Cadence Tempus
Implement and improve:
MCMM (Multi-Corner Multi-Mode) flows
SI-aware analysis (crosstalk, noise)
ECO strategies for timing closure
Ensure timing correlation between block and top level
🔹 Debug & Optimization
Perform deep analysis on:
Critical paths
False/multicycle paths
Clock domain crossings (CDC timing perspective)
Drive timing ECOs with minimal impact on power/area
Skill Requirements
Strong expertise in:
STA fundamentals (setup/hold, skew, jitter, latency)
OCV/AOCV/POCV concepts
SI effects and derates
Hands-on experience with:
Synopsys PrimeTime / Cadence Tempus
Deep understanding of:
Clock tree design and analysis
Low power (UPF/CPF) impact on timing
Advanced nodes (7nm, 5nm preferred)
Experience in hierarchical STA flows
Exposure to automation (TCL/Python scripting)
Knowledge of EM/IR and physical effects on timing
Experience working with global teams / customers
Zero/near-zero timing violations at tapeout
Clean signoff across all modes/corners
Predictable timing closure cycles
Strong correlation between block and top-level timing