Senior Design Lead - Physical Design
United States
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Job Description
Senior Design Lead - Physical Design
San Jose, California

Job Summary

  • Exposure to TSMC 2NP/3NP is must
  • Experience: 7+ years
  • BE - ECE / MTech - VLSI design 
  • Perform end‑to‑end physical design flow:
    • Floor planning
    • Power planning (PG grid, IR)
    • Placement & optimization
    • CTS (Clock Tree Synthesis)
    • Routing
    • Post‑route optimization
  • Achieve timing closure across all modes and corners
  • Resolve DRC, LVS, ERC and signoff violations
  • Handle low‑power design techniques:
    • Multi‑Vt, Multi‑voltage (UPF)
    • Power gating, clock gating
  • Perform physical verification and signoff:
    • STA (Primetime)
    • SI / Crosstalk
    • IR drop & EM analysis
  • Work on advanced nodes (7nm, 5nm, 3nm or below)
  • Collaborate with:
    • RTL & Micro‑architecture teams
    • DFT & Test engineers
    • Foundry and CAD teams
  • Debug complex timing, congestion, power, and variability issues
  • Drive methodology improvements and automation (scripts/flows)

Key Responsibilities

  • Exposure to TSMC 2NP/3NP is must
  • Experience: 7+ years
  • BE - ECE / MTech - VLSI design 
  • Perform end‑to‑end physical design flow:
    • Floor planning
    • Power planning (PG grid, IR)
    • Placement & optimization
    • CTS (Clock Tree Synthesis)
    • Routing
    • Post‑route optimization
  • Achieve timing closure across all modes and corners
  • Resolve DRC, LVS, ERC and signoff violations
  • Handle low‑power design techniques:
    • Multi‑Vt, Multi‑voltage (UPF)
    • Power gating, clock gating
  • Perform physical verification and signoff:
    • STA (Primetime)
    • SI / Crosstalk
    • IR drop & EM analysis
  • Work on advanced nodes (7nm, 5nm, 3nm or below)
  • Collaborate with:
    • RTL & Micro‑architecture teams
    • DFT & Test engineers
    • Foundry and CAD teams
  • Debug complex timing, congestion, power, and variability issues
  • Drive methodology improvements and automation (scripts/flows)

Skill Requirements

  • Exposure to TSMC 2NP/3NP is must
  • Experience: 7+ years
  • BE - ECE / MTech - VLSI design 
  • Perform end‑to‑end physical design flow:
    • Floor planning
    • Power planning (PG grid, IR)
    • Placement & optimization
    • CTS (Clock Tree Synthesis)
    • Routing
    • Post‑route optimization
  • Achieve timing closure across all modes and corners
  • Resolve DRC, LVS, ERC and signoff violations
  • Handle low‑power design techniques:
    • Multi‑Vt, Multi‑voltage (UPF)
    • Power gating, clock gating
  • Perform physical verification and signoff:
    • STA (Primetime)
    • SI / Crosstalk
    • IR drop & EM analysis
  • Work on advanced nodes (7nm, 5nm, 3nm or below)
  • Collaborate with:
    • RTL & Micro‑architecture teams
    • DFT & Test engineers
    • Foundry and CAD teams
  • Debug complex timing, congestion, power, and variability issues
  • Drive methodology improvements and automation (scripts/flows)

Other Requirements

  • Exposure to TSMC 2NP/3NP is must
  • Experience: 7+ years
  • BE - ECE / MTech - VLSI design 
  • Perform end‑to‑end physical design flow:
    • Floor planning
    • Power planning (PG grid, IR)
    • Placement & optimization
    • CTS (Clock Tree Synthesis)
    • Routing
    • Post‑route optimization
  • Achieve timing closure across all modes and corners
  • Resolve DRC, LVS, ERC and signoff violations
  • Handle low‑power design techniques:
    • Multi‑Vt, Multi‑voltage (UPF)
    • Power gating, clock gating
  • Perform physical verification and signoff:
    • STA (Primetime)
    • SI / Crosstalk
    • IR drop & EM analysis
  • Work on advanced nodes (7nm, 5nm, 3nm or below)
  • Collaborate with:
    • RTL & Micro‑architecture teams
    • DFT & Test engineers
    • Foundry and CAD teams
  • Debug complex timing, congestion, power, and variability issues
  • Drive methodology improvements and automation (scripts/flows)
Maximum Salary (US): 
Minimum Salary (US): 
Apply now
Information at a Glance

Why HCLTech?

At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first.

HCLTech is a global technology company, home to more than 223,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending June 2026 totaled $14.8 billion. 

 

Compensation and Benefits

A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year.