Job Summary
- Role: IC Packaging Design Engineer
- Project Duration: 1 year
- Start date: Beginning of Q4’26
- No of resources: 4
- Location: Chandler, AZ (primary) or Hillsboro, OR (secondary)
- Experience Tier: Senior-level (primary); Mid-level (secondary)
· Senior-Level: ~10+ years in IC packaging / package design
· Mid-Level: 4–6+ years (MS) or 6+ years (BS) in IC packaging / package design
- Education: Bachelor’s or Master’s degree in Electrical /Electronics Engineering
- Experience:
· Strong hands-on experience in Siemens (Mentor) Xpedition (XPD); Alternatively: Cadence Allegro/Advanced Package Designer (APD / SiP)
· Candidates should have experience in the below domains:
o Physical Design & Layout
o Substrate design and layout
o SI/PI aware design implementation
o Design for performance, manufacturability, yield, and reliability
o Design rule compliance
Key Responsibilities
2. To lead a team of designers, provide guidance, and ensuring the delivery of high-quality design solutions in alignment with the overall business goals.
3. To present design concepts and play a crucial role in shaping the overall design vision and strategy.
4. To stay abreast of industry trends, emerging technologies to drive innovation and excellence in design.