Job Summary
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Signal & power Integrity experience is mandatory |
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6-8 yrs of Strong experience in Signal Integrity and Power Integrity fundamental concepts. |
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Deep Understanding of S-parameter & its modelling concepts for Single ended and differential interfaces. |
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Experience in simulating (FD/TD) memory interfaces for Board and Package is required (DDR4/LPDDR4) |
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Experience in simulating (FD/TD) High Speed Serial IO interfaces for Board and Package is required (PCIe Gen3/4, SATA Gen3, USB3/3.1 and Display Interfaces etc.) |
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Good knowledge of Power Delivery Network, impedance profile analysis, IR Drop Analysis, and time domain Analysis. |
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Experience in extracting the PDN model of package and PCB power rails and perform decoupling capacitor optimization, Loop inductance analysis. |
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Strong knowledge in simulation tools specifically Hspice, Sigrity (2.5D and 3D-EM Must), ADS and other tools like Ansys SIwave, HFSS 3D. Cadence- PowerSI & PowerDC |
Key Responsibilities
2. To lead a team of designers, provide guidance, and ensuring the delivery of high-quality design solutions in alignment with the overall business goals.
3. To present design concepts and play a crucial role in shaping the overall design vision and strategy.
4. To stay abreast of industry trends, emerging technologies to drive innovation and excellence in design.