Job Summary

B.Tech/ M.Tech with 4 to 8 years of experience exclusively in DFT.
Sub-system level: Hands-on experience to do scan insertion, ATPG coverage improvement, Pattern Generation/Simulation. Should have expertise on Simulation debug No-timing/Timing.
"Sub-system level: Hands-on Experience to do MBIST Insertion, Verification, Pattern generation. Thorough with Diagnostics and Repairability concepts.
Good to have functional & integration knowledge of TAP controllers and JTAG. Working knowledge of JTAG, iJTAG, ICL, PDL etc."
"DFX and DFD feature insertion and verification at SS level. SOC level verification for the same.
QC checks post RTL insertion, SpyGlass, CDC, RDC, VCLP etc."
Capable of doing SOC level verification, Pattern sim and delivery. 
Should be able to handle cluster team of 2-3 members.
Must be aware of interface to ATEs, tester hand-off languages/TDL/Verilog and must know to drive/modify test procedures. Desirable to have experience in Post Silicon Debug on Tester.
Good at Communication. Compatible of working Remotely / Hybrid method with multiple sites.

Key Responsibilities

1. To leverage design expertise to ensure that software and products exhibit user-friendliness, intuitiveness, and alignment with user expectations, contributing to the creation of seamless user experiences.
2. To lead a team of designers, provide guidance, and ensuring the delivery of high-quality design solutions in alignment with the overall business goals.
3. To present design concepts and play a crucial role in shaping the overall design vision and strategy.
4. To stay abreast of industry trends, emerging technologies to drive innovation and excellence in design.

Skill Requirements

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Other Requirements

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