Job Summary

We are seeking a SoC Design Verification Lead with 8-15 years of experience in ASIC/SoC verification to lead end-to-end verification activities for complex SoC programs. The candidate will be responsible for verification strategy, testbench architecture, verification closure, and mentoring the verification team through tape-out.

Key Responsibilities

Key Responsibilities

• Lead SoC verification activities from specification review to tape-out.
• Define verification plans, methodologies, and full-chip verification strategies.
• Architect and develop reusable SystemVerilog/UVM based verification environments.
• Drive constrained-random verification, regression execution, coverage closure, and sign-off.
• Develop and review functional coverage models and SystemVerilog Assertions (SVA).
• Lead debug of complex SoC verification issues and drive bug closure.
• Develop and debug SoC-level C/SV testbench components and C-based test cases.
• Collaborate with RTL, Architecture, Firmware, DFT, and Validation teams.
• Mentor and guide verification engineers while ensuring project milestones are met.

Skill Requirements

Required Skills

• Strong expertise in SystemVerilog, UVM/OVM, and ASIC/SoC verification methodologies.
• Hands-on experience in SoC Testbench Architecture and reusable verification environment development.
• Experience with functional coverage, assertions (SVA), and coverage-driven verification.
• Strong debugging skills using Verdi, DVE, SimVision, or equivalent tools.
• Experience in C/C++ based verification and SoC-level test development.
• Good understanding of ASIC/SoC lifecycle with participation in multiple tape-outs.
• Exposure to industry-standard protocols such as AXI, AHB, APB, PCIe, USB, Ethernet, etc.

Preferred Skills

• Experience in Emulation/FPGA Prototyping.
• Low Power Verification (UPF/CPF).
• Verification automation using Python/Perl/Shell scripting.
• Experience leading small to medium verification teams.

Other Requirements