Job Summary
Key roles include guiding PPA optimization, leading timing sign-off, and directing tape-out milestones.
Familiarity of the below tools like
Design Compiler, Fusion Compiler, PrimeTime, ICC2, StarRC, VC SpyGlass.
He/She should understand how decisions made at the RTL stage affect synthesis, timing, power, congestion, testability, and physical implementation.
He/She need to anticipate downstream issues early, coordinate across all design functions, drive timing/power/area (PPA) optimization holistically, and lead the team through signoff and successful tape-out.
Key Responsibilities
• Team Leadership: Good to have team lead skills like Mentoring engineers, assigning tasks, and track project convergence metrics.
• Flow Execution: Must have good experience in Synthesis, Constraints generation, LEC, STA. Good to have PD execution experience like owning block - floorplanning, place-and-route (PnR), and clock tree synthesis (CTS).
• Sign-off and Verification: Drive static timing analysis (STA), physical verification (DRC/LVS), and low-power checks.
• Cross-Functional Collaboration: Coordinate with RTL, DFT, and EDA vendors to resolve bottlenecks.
Requirements and Qualifications
• Experience: 5 to 10 years in semiconductor physical design with tape-out success.
• Technical Mastery: Deep expertise in advanced process nodes and EDA tools (e.g. Synopsys IC Compiler, PrimeTime).
• Education: Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
• Soft Skills: Strong project management, communication, and debugging capabilities
Key Responsibilities
2. To lead a team of designers, provide guidance, and ensuring the delivery of high-quality design solutions in alignment with the overall business goals.
3. To present design concepts and play a crucial role in shaping the overall design vision and strategy.
4. To stay abreast of industry trends, emerging technologies to drive innovation and excellence in design.