Job Summary
Own the custom analog and mixed signal layout of critical analog blocks for LPDDR PHYs, including critical Datapath, bias networks, IO analog frontends, and reference circuits, ensuring robustness across PVT, low noise coupling, and high matching accuracy.
Complete high‑speed LPDDR interface layout (LPDDRx), addressing signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity in advanced nodes.
Build and optimize array‑based layouts for LPDDR DQ/DQS byte lanes, CA lanes, and replica paths, ensuring strict symmetry, pitch matching, repeatability, and scalability across multi‑byte and multi‑channel configurations.
Implement custom digital block layouts within the LPDDR PHY, including training logic, calibration engines, and test/debug circuitry, with careful consideration of clocking, congestion, and interaction with sensitive analog regions.
Drive layout‑aware co‑building with circuit designers to meet timing, noise, IR, and EM requirements for mixed‑signal LPDDR blocks, incorporating parasitic awareness early in the design cycle.
Apply guidelines for power distribution, grounding, and isolation, including guard rings, deep‑N‑well usage, decoupling strategies, and domain separation to protect critical analog and high‑speed signals.
Perform DRC/LVS closure, parasitic extraction reviews, and correlation with simulation results to ensure silicon‑accurate performance of high‑speed and analog‑intensive LPDDR blocks.
Support post‑layout optimization and ECOs, resolving issues related to margin degradation, yield, and manufacturability while maintaining JEDEC compliance.
Work in close partnership with architecture, circuit, verification, and silicon debug groups to ensure first-silicon success and high-volume manufacturability of LPDDR products.
Contribute to PPA optimization with a strong focus on low‑power operation, area efficiency, and reliability requirements specific to LPDDR applications.
Foster a culture of knowledge sharing and continuous improvement, contributing to VXL‑compatible layout flows, guidelines, and build reviews that enable first‑silicon success.
Leverage AI/ML knowledge as a benefit to support data‑driven optimization, layout automation initiatives, and improved debug and correlation workflows.
Leveraging Artificial Intelligence.