Job Summary
Design Lead - Analog Layout Design
Experience
4.5 – 7 years of relevant industry experience in Analog/Mixed-Signal Layout Design.
Experience in one or more of the following domains:
Power Management
Data Converters
High-Speed Analog
IO Layout
Clocking Solutions
Custom IP Development.
EDA Tools
Layout Editor: Cadence Virtuoso / Synopsys Custom Compiler
Physical Verifications: Calibre / PVS / Assura / ICV
EM-IR: Voltus / Totem / mPower
Education
B.Tech / M.Tech in Electrical or Electronics Engineering.
Key Responsibilities
Drive block and macro-level physical layout for analog/mixed-signal blocks (e.g., PLLs, ADCs, DACs, LDOs) and custom digital circuits in advanced FinFET/Planar technology nodes.
Run and debug physical verification checks including DRC, LVS, ERC, EM/IR drop, and DFM to ensure high first-time tape-out success.
Collaborate with Place & Route (P&R) and circuit design teams to resolve full-chip integration issues, floorplanning, and macro placements.
Guide, train, and mentor junior layout engineers to foster skill development and ensure delivery schedules are met.
Improve custom layout methodologies, optimize parasitic extraction techniques, and automate routine tasks
Process Nodes Experience
Hands-on experience in one or more of the following technologies is preferred:
Intel Advanced Nodes
TSMC N16 / N7 / N5 / N3
Samsung Advanced Process Nodes
Global Foundries Technologies
Any BCD or Bi-CMOS process nodes.
Scripting
Basic programming or scripting skills in one of the below programming languages is highly preferred
SKILL / SHELL / PERL / TCL