Job Summary
JD for STA: Experience: 5+ years Own full-chip STA signoff for all PVT corners and modes (functional, scan, low-power, etc.) Drive timing closure at chip level, including setup/hold, noise, OCV/AOCV/POCV Analyze and resolve timing violations across hierarchical boundaries 🔹 Constraint Management Define and validate SDC constraints for chip-level integration Ensure proper timing budgeting and partitioning across blocks Review and align block-level constraints with chip-level requirements 🔹 Signoff & Methodology Lead signoff STA using tools like: Synopsys PrimeTime Cadence Tempus Implement and improve: MCMM (Multi-Corner Multi-Mode) flows SI-aware analysis (crosstalk, noise) ECO strategies for timing closure Ensure timing correlation between block and top level 🔹 Debug & Optimization Perform deep analysis on: Critical paths False/multicycle paths Clock domain crossings (CDC timing perspective) Drive timing ECOs with minimal impact on power/area 🔸Strong expertise in: STA fundamentals (setup/hold, skew, jitter, latency) OCV/AOCV/POCV concepts SI effects and derates Hands-on experience with: Synopsys PrimeTime / Cadence Tempus Deep understanding of: Clock tree design and analysis Low power (UPF/CPF) impact on timing Advanced nodes (7nm, 5nm preferred) Experience in hierarchical STA flows Exposure to automation (TCL/Python scripting) Knowledge of EM/IR and physical effects on timing Experience working with global teams / customers Zero/near-zero timing violations at tapeout Clean signoff across all modes/corners Predictable timing closure cycles Strong correlation between block and top-level timing -------------------------------------- JD for EMIR: Experience: 5+ years Experience with ASIC EM IR tools: RHSC and/or Voltus is MUST. Enabling ASIC EMIR tools for new process node and latest technology features. Detailed knowledge of EMIR concepts and working of ASIC EMIR tool is a must. Creating reference flows that act as test vehicles to evaluate tools and EM tech files, PDK collaterals (precisely RV techfiles). Develop and automate workflows to enhance the efficiency and accuracy of EM IR analysis. Any automation language is must (Preferably python, perl and tcl) Debug and troubleshoot design challenges related to EM IR, providing innovative solutions. Write good documents for ASIC EMIR flows and PDK. Train the users and design engineers on ASIC flows and tech file usage. ---------------------------------------- JD for FEV : Experience: 5+ years Experience with Formal Equivalence Verification (FEV) tools is a must Execute RTL ↔ Netlist, Netlist ↔ Netlist, and ECO FEV at block and full-chip levels Debug and resolve non-equivalence failures, aborted points, and compare issues due to synthesis, ECO, scan, and DFT logic Create and maintain reference FEV flows and testcases to validate tool features and methodologies Develop and automate workflows to improve efficiency and runtime of FEV signoff. Automation using Python/ Perl/Tcl is preferred Work closely with RTL, Synthesis, DFT, and Physical Design teams for issue closure. Generate signoff-ready reports and ensure adherence to project signoff criteria Write clear documentation for FEV flows and train users on tool usage and best practices ---------------------------------------- JD for VCLP : Experience: 5+ years Experience with Vectorless Low Power (VCLP/CLP) tools is a must Enable and execute UPF-based low-power verification at block and full-chip levels Validate power intent correctness including isolation, retention, level shifters, power switches, and always-on logic Debug and resolve low-power violations related to missing/incorrect UPF definitions and design connectivity Create reference low-power flows and testcases to evaluate tools, PDKs, and EM/LP-related collateral Develop and automate VCLP workflows to enhance accuracy and reduce runtime of VCLP signoff. Automation using Python/Perl/Tcl is preferred Collaborate with RTL, PD, and Power Architecture teams to close lowpowe
Key Responsibilities
JD for STA: Experience: 5+ years Own full-chip STA signoff for all PVT corners and modes (functional, scan, low-power, etc.) Drive timing closure at chip level, including setup/hold, noise, OCV/AOCV/POCV Analyze and resolve timing violations across hierarchical boundaries 🔹 Constraint Management Define and validate SDC constraints for chip-level integration Ensure proper timing budgeting and partitioning across blocks Review and align block-level constraints with chip-level requirements 🔹 Signoff & Methodology Lead signoff STA using tools like: Synopsys PrimeTime Cadence Tempus Implement and improve: MCMM (Multi-Corner Multi-Mode) flows SI-aware analysis (crosstalk, noise) ECO strategies for timing closure Ensure timing correlation between block and top level 🔹 Debug & Optimization Perform deep analysis on: Critical paths False/multicycle paths Clock domain crossings (CDC timing perspective) Drive timing ECOs with minimal impact on power/area 🔸Strong expertise in: STA fundamentals (setup/hold, skew, jitter, latency) OCV/AOCV/POCV concepts SI effects and derates Hands-on experience with: Synopsys PrimeTime / Cadence Tempus Deep understanding of: Clock tree design and analysis Low power (UPF/CPF) impact on timing Advanced nodes (7nm, 5nm preferred) Experience in hierarchical STA flows Exposure to automation (TCL/Python scripting) Knowledge of EM/IR and physical effects on timing Experience working with global teams / customers Zero/near-zero timing violations at tapeout Clean signoff across all modes/corners Predictable timing closure cycles Strong correlation between block and top-level timing -------------------------------------- JD for EMIR: Experience: 5+ years Experience with ASIC EM IR tools: RHSC and/or Voltus is MUST. Enabling ASIC EMIR tools for new process node and latest technology features. Detailed knowledge of EMIR concepts and working of ASIC EMIR tool is a must. Creating reference flows that act as test vehicles to evaluate tools and EM tech files, PDK collaterals (precisely RV techfiles). Develop and automate workflows to enhance the efficiency and accuracy of EM IR analysis. Any automation language is must (Preferably python, perl and tcl) Debug and troubleshoot design challenges related to EM IR, providing innovative solutions. Write good documents for ASIC EMIR flows and PDK. Train the users and design engineers on ASIC flows and tech file usage. ---------------------------------------- JD for FEV : Experience: 5+ years Experience with Formal Equivalence Verification (FEV) tools is a must Execute RTL ↔ Netlist, Netlist ↔ Netlist, and ECO FEV at block and full-chip levels Debug and resolve non-equivalence failures, aborted points, and compare issues due to synthesis, ECO, scan, and DFT logic Create and maintain reference FEV flows and testcases to validate tool features and methodologies Develop and automate workflows to improve efficiency and runtime of FEV signoff. Automation using Python/ Perl/Tcl is preferred Work closely with RTL, Synthesis, DFT, and Physical Design teams for issue closure. Generate signoff-ready reports and ensure adherence to project signoff criteria Write clear documentation for FEV flows and train users on tool usage and best practices ---------------------------------------- JD for VCLP : Experience: 5+ years Experience with Vectorless Low Power (VCLP/CLP) tools is a must Enable and execute UPF-based low-power verification at block and full-chip levels Validate power intent correctness including isolation, retention, level shifters, power switches, and always-on logic Debug and resolve low-power violations related to missing/incorrect UPF definitions and design connectivity Create reference low-power flows and testcases to evaluate tools, PDKs, and EM/LP-related collateral Develop and automate VCLP workflows to enhance accuracy and reduce runtime of VCLP signoff. Automation using Python/Perl/Tcl is preferred Collaborate with RTL, PD, and Power Architecture teams to close lowpowe