Job Summary
The Memory Layout Engineer will develop and integrate full-custom layouts for digital and analog sections of MRAM memories. The role covers memory building blocks, top-level integration, parasitic extraction, physical verification, manufacturability, yield, and power/signal-integrity considerations. The successful candidate will combine strong hands-on layout execution with disciplined verification and cross-functional communication.Key ResponsibilitiesCreate P-cell-based layouts for digital and analog portions of MRAM memory designs.Develop physical layouts for bit-cell arrays, row decoders, column decoders, sense amplifiers, and input/output blocks.Integrate memory sub-blocks into complete top-level memory layouts while maintaining hierarchy, connectivity, and design intent.Perform layout parasitic extraction (LPE) and support layout modifications required to achieve performance targets.Execute physical verification, including Design Rule Check (DRC) and Layout Versus Schematic (LVS).Apply Design for Manufacturability (DFM) and Design for Yield (DFY) principles throughout layout implementation and sign-off.Analyze potential electromigration, IR-drop, power-integrity, and signal-integrity risks, and implement layout improvements as required.Develop or maintain productivity scripts in PERL, Shell, TCL, or Cadence SKILL where useful.Collaborate with circuit design, verification, and process teams to resolve layout issues and support design closure.Required QualificationsBachelor's degree in Electrical Engineering, Computer Engineering, or a related discipline.At least 5 years of relevant experience in IC or memory layout engineering.Practical experience with memory layout using Cadence Virtuoso and physical verification using Cadence Assura and/or Siemens Calibre.Understanding of memory compiler architecture and major memory sub-blocks.Experience in DRC, LVS, LPE, DFM, and EM/IR analysis.Strong analytical, troubleshooting, communication, and teamwork capabilities.Ability to work professionally in both Chinese and English.Preferred ExperienceHands-on MRAM memory layout experience.Experience with low-power, high-performance, or high-density SRAM design.Exposure to multiple semiconductor technology nodes.Experience with Cadence Voltus and Synopsys StarRC.Scripting experience in PERL, Shell, TCL, or Cadence SKILL.Search KeywordsMemory Layout • MRAM • SRAM • Cadence Virtuoso • Assura • Siemens Calibre • StarRC • Voltus • DRC • LVS • LPE • DFM • DFY • EM/IR
Key Responsibilities
The Memory Layout Engineer will develop and integrate full-custom layouts for digital and analog sections of MRAM memories. The role covers memory building blocks, top-level integration, parasitic extraction, physical verification, manufacturability, yield, and power/signal-integrity considerations. The successful candidate will combine strong hands-on layout execution with disciplined verification and cross-functional communication.Key ResponsibilitiesCreate P-cell-based layouts for digital and analog portions of MRAM memory designs.Develop physical layouts for bit-cell arrays, row decoders, column decoders, sense amplifiers, and input/output blocks.Integrate memory sub-blocks into complete top-level memory layouts while maintaining hierarchy, connectivity, and design intent.Perform layout parasitic extraction (LPE) and support layout modifications required to achieve performance targets.Execute physical verification, including Design Rule Check (DRC) and Layout Versus Schematic (LVS).Apply Design for Manufacturability (DFM) and Design for Yield (DFY) principles throughout layout implementation and sign-off.Analyze potential electromigration, IR-drop, power-integrity, and signal-integrity risks, and implement layout improvements as required.Develop or maintain productivity scripts in PERL, Shell, TCL, or Cadence SKILL where useful.Collaborate with circuit design, verification, and process teams to resolve layout issues and support design closure.Required QualificationsBachelor's degree in Electrical Engineering, Computer Engineering, or a related discipline.At least 5 years of relevant experience in IC or memory layout engineering.Practical experience with memory layout using Cadence Virtuoso and physical verification using Cadence Assura and/or Siemens Calibre.Understanding of memory compiler architecture and major memory sub-blocks.Experience in DRC, LVS, LPE, DFM, and EM/IR analysis.Strong analytical, troubleshooting, communication, and teamwork capabilities.Ability to work professionally in both Chinese and English.Preferred ExperienceHands-on MRAM memory layout experience.Experience with low-power, high-performance, or high-density SRAM design.Exposure to multiple semiconductor technology nodes.Experience with Cadence Voltus and Synopsys StarRC.Scripting experience in PERL, Shell, TCL, or Cadence SKILL.Search KeywordsMemory Layout • MRAM • SRAM • Cadence Virtuoso • Assura • Siemens Calibre • StarRC • Voltus • DRC • LVS • LPE • DFM • DFY • EM/IR