Job Summary
Digital Logic Verification Engineer responsible for verifying FPGA-based digital designs and ensuring high-quality, robust implementations. The role focuses on SystemVerilog/UVM verification, testbench development, coverage closure, debugging, and RTL verification, while collaborating closely with FPGA designers and cross-functional engineering teams.
Key Responsibilities
Review FPGA design requirements and technical specifications.
Develop and review verification plans and test strategies.
Design and implement SystemVerilog/UVM testbench architectures.
Develop reference models, test cases, and verification environments.
Debug simulation and design issues and support root cause analysis.
Collect, analyze, and achieve closure of functional and code coverage.
Track and manage defects using issue-tracking tools.
Collaborate closely with FPGA/RTL logic designers.
Communicate verification progress, technical risks, and issues to technical leads.
Support continuous verification activities within CI/CD workflows.
Skill Requirements
3+ years of professional experience in digital logic/FPGA verification or related roles.
Strong hands-on experience with SystemVerilog and UVM.
Experience with Cadence Xcelium or similar industry-standard simulators.
Experience in Verilog HDL and RTL design.
Knowledge of common protocols such as SPI, AXI, and DDR.
Familiarity with SystemVerilog Assertions (SVA) and assertion-based verification.
Experience with functional coverage, code coverage, simulation, and debugging.
Experience working with CI/CD development flows.
FPGA design experience is an added advantage.