Job Summary
Good understanding of ASIC/SoC life cycle Has participated in multiple ASIC/SoC verification till tapeout stage Experience writing ASIC/SoC testplans 1.Experience in ASIC/SoC Testbench definition 2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM). 1. Experience in developing TB components for SOC with C, SV 1.Expertise & hands-on experience in OVM
Key Responsibilities
1. To architect| design and develop (through Team) solution for product/project & sustenance delivery
2. To bridge the gap between client needs and business goals by gathering requirements, crafting innovative solutions with deep domain/technology expertise, and driving successful implementations that propel strategic initiatives.
3. To ensure knowledge up-gradation and work with new technologies so that the solution is current and meets quality standards and the client requirements
4. To review architecture and design deliverables and ensure solutions adhere to industry best practices ,architectural standards simultaneously establish and enforce governance /compliance measures.
5. To train and develop team so as to ensure that there is an adequate supply of trained manpower in the said technology and delivery risks are mitigated
6. To submit Whitepapers, participate in industry forums and file Patents