Job Summary

Candidates with minimum 15 years experience is mandatory
Experience in defining micro-architecture specifications for high-performance, low-power digital design blocks and subsystems.
Establish, standardize, and continuously improve engineering methodologies, automation scripts, and best practices across the organization.
Experience in Full chip RTL integration
Experience with ASIC/SoC development flow including synthesis/timing constraints development, Static Timing Analysis closure, resolving P& R congestion issues etc. 
Experience in RTL Synthesis
Scripting experience
Experience integrating IP's like PCIe, DDR, Ethernet etc.
Should be able to lead a team of 5 to 6 leads under whom entry level engineers will be there. 
Expected to handle minimum 3 projects simultaneously 
Experience in handling  and interacting with clients across different Geos.
Excellent communication skills are mandatory. 
Should be able to interact with leads of different disciplines and able to work in a collabarative manner with different SPOCs

Key Responsibilities

Skill Requirements

Other Requirements