Job Summary
Own full-chip STA signoff for all PVT corners and modes (functional, scan, low-power, etc.)
Drive timing closure at chip level, including setup/hold, noise, OCV/AOCV/POCV
Analyze and resolve timing violations across hierarchical boundaries
🔹 Constraint Management
Define and validate SDC constraints for chip-level integration
Ensure proper timing budgeting and partitioning across blocks
Review and align block-level constraints with chip-level requirements
🔹 Signoff & Methodology
Lead signoff STA using tools like:
Synopsys PrimeTime
Cadence Tempus
Implement and improve:
MCMM (Multi-Corner Multi-Mode) flows
SI-aware analysis (crosstalk, noise)
ECO strategies for timing closure
Ensure timing correlation between block and top level
🔹 Debug & Optimization
Perform deep analysis on:
Critical paths
False/multicycle paths
Clock domain crossings (CDC timing perspective)
Drive timing ECOs with minimal impact on power/area
🔸Strong expertise in:
STA fundamentals (setup/hold, skew, jitter, latency)
OCV/AOCV/POCV concepts
SI effects and derates
Hands-on experience with:
Synopsys PrimeTime / Cadence Tempus
Deep understanding of:
Clock tree design and analysis
Low power (UPF/CPF) impact on timing
Advanced nodes (7nm, 5nm preferred)
Experience in hierarchical STA flows
Exposure to automation (TCL/Python scripting)
Knowledge of EM/IR and physical effects on timing
Experience working with global teams / customers
Zero/near-zero timing violations at tapeout
Clean signoff across all modes/corners
Predictable timing closure cycles
Strong correlation between block and top-level timing
Key Responsibilities
2. To bridge the gap between client needs and business goals by gathering requirements, crafting innovative solutions with deep domain/technology expertise, and driving successful implementations that propel strategic initiatives.
3. To ensure knowledge up-gradation and work with new technologies so that the solution is current and meets quality standards and the client requirements
4. To review architecture and design deliverables and ensure solutions adhere to industry best practices ,architectural standards simultaneously establish and enforce governance /compliance measures.
5. To train and develop team so as to ensure that there is an adequate supply of trained manpower in the said technology and delivery risks are mitigated
6. To submit Whitepapers, participate in industry forums and file Patents