Job Summary
| Perform end‑to‑end physical design flow: |
| Floorplanning |
| Power planning (PG grid, IR) |
| Placement & optimization |
| CTS (Clock Tree Synthesis) |
| Routing |
| Post‑route optimization |
| Achieve timing closure across all modes and corners |
| Resolve DRC, LVS, ERC and signoff violations |
| Handle low‑power design techniques: |
| Multi‑Vt, Multi‑voltage (UPF) |
| Power gating, clock gating |
| Perform physical verification and signoff: |
| STA (Primetime) |
| SI / Crosstalk |
| IR drop & EM analysis |
| Work on advanced nodes (7nm, 5nm, 3nm or below) |
| Collaborate with: |
| RTL & Micro‑architecture teams |
| DFT & Test engineers |
| Foundry and CAD teams |
| Debug complex timing, congestion, power, and variability issues |
| Drive methodology improvements and automation (scripts/flows) |
Key Responsibilities
2. Develop And Validate Prototypes Using Physical Design Tools Such As Synopsys Ic Compiler And Cadence Innovus, Ensuring Design Decisions Meet Performance And Functionality Criteria.
3. Mentor And Guide Junior Designers By Sharing Expertise Through Training Sessions And Creating Detailed Documentation To Enhance Team Knowledge.
4. Work Closely With Cross-Functional Teams, Including Hardware And Software Engineers, To Ensure Alignment Of Physical Design With Overall Project Goals And Objectives.
5. Partner With Quality Assurance Teams To Implement And Maintain Rigorous Testing Processes, Ensuring The Delivery Of High-Quality Designs That Meet Industry Standards.
Skill Requirements
2. Proficiency In Using Design Software Such As Cadence, Synopsys, Or Mentor Graphics.
3. Familiarity With Semiconductor Design Principles And Practices.
4. Excellent Communication Skills To Effectively Interact With Stakeholders And Team Members.