Job Summary
The Senior RTL Design Engineer plays a crucial role in delivering high-quality designs that align with project objectives and customer requirements. This role requires a strong understanding of RTL design principles and the ability to collaborate effectively with various stakeholders to refine design specifications, ensuring consistency and excellence in the overall design vision.
Key Responsibilities
1. Collaborate With Stakeholders To Gather And Refine Rtl Design Requirements, Ensuring Clear Understanding And Alignment With Project Goals.
2. Develop And Implement Prototypes And Proof-Of-Concept Designs Using Vhdl/Verilog, Validating Design Decisions Against Project Specifications.
3. Mentor And Guide Junior Designers By Sharing Knowledge And Expertise Through Structured Training Sessions And Comprehensive Documentation.
4. Work Closely With Cross-Functional Teams To Ensure That Rtl Design Integrates Seamlessly With Overall Project Architectures And Goals.
5. Partner With Quality Assurance Teams To Define Testing Plans And Methodologies, Ensuring The Delivery Of High-Quality Rtl Designs That Meet Industry Standards.
Skill Requirements
1. Strong Understanding Of Rtl Design Principles And Methodologies.
2. Proficient In Vhdl/Verilog For Digital Design And Simulation.
3. Familiarity With Fpga And Asic Design Flows And Tools.
4. Good Communication Skills To Interact Effectively With Stakeholders And Team Members.
1.Analyze and migrate legacy FPGA designs from AHDL to Verilog. Ensure functional equivalence and optimized design performance post-migration.
2.Perform synthesis and generate FPGA programming files using Intel Quartus tool.
3.Ensure timing closure and optimal resource utilization.
4.Support FPGA board bring-up and HW testing.
5.Validate FPGA functionality on target hardware platforms & debug issues using lab instruments (oscilloscope, logic analyzer).
6.Document design changes & migration details
7.Strong expertise in Verilog HDL (mandatory) & Working knowledge of AHDL (legacy design understanding)
8.Experience with Intel/Altera FPGA tools (Quartus Prime)
9.Solid understanding of Digital design fundamentals, RTL design, timing analysis and constraints
10.Familiarity with interfaces like SPI & UART
Other Requirements
2. Optional But Valuable: Completion Of Relevant Training Courses In Digital Design And Verification Methodologies.