Job Summary

The DFT Architect will be responsible for defining, driving, and governing the complete Design-for-Test (DFT) strategy for complex SoCs delivered under a turnkey/outcome-based engagement model. The role owns DFT architecture from feasibility through silicon bring-up, ensuring testability, manufacturability, quality, coverage, schedule adherence, and customer acceptance.

The architect serves as the technical authority for all DFT-related decisions and works closely with SoC Architects, RTL, Integration, Verification, Physical Design, STA, Packaging, ATE, Product Engineering, and Foundry teams

DFT Architecture & Strategy

• Define SoC-level DFT architecture and test strategy during feasibility and architecture phases.
• Create DFT specifications, test architecture documents, and implementation guidelines.
• Establish hierarchical DFT methodology across IP, Subsystems, and SoC.
• Drive testability requirements into architecture and micro-architecture reviews.
• Define scan partitioning, test access mechanisms, compression strategy, and test modes.
• Define manufacturing test, diagnostics, and yield enhancement strategy.

DFT Planning & Technical Leadership

• Own DFT estimation, planning, risks, schedules, and milestone tracking.
• Review third-party IP test readiness and integration requirements.
• Lead DFT design reviews and sign-off reviews.
• Drive customer discussions and provide technical guidance.
• Mentor DFT engineers, leads, and subsystem owners.

DFT Implementation Ownership

• Drive implementation of:
• Scan Insertion
• EDT/Test Compression
• MBIST
• LBIST
• Boundary Scan (IEEE 1149.1/1149.6)
• IJTAG/IEEE 1687
• OCC (On-Chip Clock Controller)
• Test Point Insertion
• SSN (Streaming Scan Network)
• High-Speed Interface Testing
• Security-aware DFT features
• Resolve complex DRC and testability issues.
• Ensure DFT compliance across large multi-power and multi-clock SoCs.

Key Responsibilities

ATPG & Coverage Closure

• Own ATPG methodology and sign-off.
• Drive stuck-at, transition, path-delay, cell-aware, and bridge fault coverage closure.
• Analyze coverage loss and implement improvement strategies.
• Define diagnostic pattern generation methodology.
• Review test quality metrics and coverage goals.

DFT Verification & Sign-off

• Define DFT verification strategy.
• Review:
• DFT RTL verification
• Gate-Level Simulations
• Test Mode Verification
• Test Timing Verification
• Formal Equivalence
• DFT CDC requirements
• Ensure sign-off quality prior to tape-out.

Physical Design & STA Collaboration

• Work closely with PD teams on:
• Scan chain optimization
• OCC implementation
• Test clock architecture
• Test-mode timing closure
• Congestion and routing impacts
• Ensure DFT-aware floorplanning and implementation.

Test Program & Silicon Readiness

• Partner with Product Engineering and ATE teams.
• Define pattern handoff strategy.
• Support tester pattern generation and debug.
• Review production test flows.
• Lead silicon bring-up DFT debug.
• Drive yield improvement initiatives and diagnosis activities.

Turnkey Program Responsibilities

• Participate in:
• Feasibility Review
• Project Kickoff
• Design Kickoff
• Architecture Reviews
• Milestone Sign-offs
• Change Control Board Reviews
• Own DFT delivery quality, schedule, and customer commitments.
• Support program risk assessment and mitigation planning.
• Contribute to project execution methodology and best practices. [Turnkey FP...amework_v1 | Word], [BI-WEEKLY_...G2026_v3.1 | PowerPoint]

Skill Requirements

Mandatory Technical Skills Required :-    18-25 years of DFT experience.

• Multiple successful SoC tape-outs.
• Expertise in:
• Scan
• MBIST
• ATPG
• EDT/Test Compression
• LBIST
• Boundary Scan
• OCC
• DFX methodologies
• Strong understanding of:
• RTL Design
• SoC Integration
• Physical Design
• STA
• Low Power Architectures
• Multi-clock and Multi-power SoCs
• Experience with advanced nodes (16nm and below preferred).

EDA Tools

• Synopsys DFT Compiler
• Tessent Suite
• Modus
• TetraMAX/TestMAX
• ATPG Tools
• Spyglass DFT
• PrimeTime
• Genus/Design Compiler
• Innovus/Fusion Compiler
• Verdi

Other Requirements

Desirable

• Automotive (ISO 26262) DFT methodologies.
• Safety and diagnostic coverage analysis.
• Advanced packaging/chiplet test strategies.
• Silicon debug and yield ramp expertise.
• Analog/Mixed Signal DFT experience (PLL, DDR, MIPI, ADC/DAC, SerDes, USB). [HCLTech_se...s_detailed | PowerPoint], [Capability Deck_v1 | PowerPoint], [HCLTech Te...March 2026 | PowerPoint]

Leadership Expectations

• Technical owner for DFT workstream in a turnkey SoC program.
• Lead teams of 10-50+ DFT engineers across geographies.
• Interface directly with customer architects and management.
• Drive technical decisions impacting schedule, quality, and manufacturability.
• Establish reusable DFT methodology, automation, and best practices.
• Mentor future DFT leads and architects.

Success Metrics

• Test Coverage Achievement (>95% Stuck-at, >90% Transition as program targets).
• Zero critical DFT escapes at tape-out.
• First-pass silicon success.
• DFT milestone adherence.
• Yield ramp support effectiveness.
• Customer satisfaction and technical acceptance.
• Reuse and standardization across programs. [HCLTech Te...March 2026 | PowerPoint], [Capability Deck_v1 | PowerPoint]