Job Summary
Lead and own chip-level verification strategy and execution for complex SoCs, ensuring functional correctness, coverage closure, and high-quality tapeouts. This role requires deep expertise in system-level verification, integration challenges, and leadership across multiple IP/block teams.
🎯 Key Responsibilities
🔹 Verification Ownership
Own end-to-end chip-level DV from planning to signoff
Define and drive verification strategy, including reuse of block-level environments
Ensure functional correctness of integrated SoC across all subsystems
🔹 Testbench & Methodology
Architect and develop scalable chip-level testbenches (typically UVM-based)
Drive reuse and integration of block/IP-level verification environments
Ensure best practices in:
Stimulus generation
Scoreboarding
Assertions (SVA)
Coverage models
🔹 Integration & Debug
Handle complex SoC integration issues:
Interface mismatches
Protocol violations
Reset/boot sequence issues
Lead debug of system-level failures and root cause analysis
Work closely with RTL, architecture, and firmware teams
🔹 Coverage Closure
Define and track:
Functional coverage
Code coverage (line/toggle/branch/FSM)
Drive closure to meet tapeout criteria
Identify and close coverage holes and corner cases
Key Responsibilities
Cross-Functional Collaboration
Collaborate with:
RTL design teams
Firmware/software teams (for boot/use-case validation)
Emulation/FPGA teams
Post-silicon validation teams
Ensure alignment between pre-silicon and post-silicon validation plans
🔹 Platform & Performance
Enable verification on:
Simulation platforms
Emulation (Palladium/Zebu)
FPGA prototyping (optional)
Optimize regression performance and turnaround time
🔹 Leadership
Lead and mentor a team of DV engineers
Drive verification planning, reviews, and signoff
Define quality metrics, schedules, and execution tracking
Act as single point of ownership for DV signoff
🧰 Required Skills & Expertise
🔸 Technical
Strong expertise in:
SystemVerilog & UVM methodology
Assertions (SVA)
Functional coverage
Experience in:
SoC-level verification
Complex protocols (AXI, PCIe, DDR, etc.)
Solid understanding of:
Computer architecture / SoC architecture
Low-power verification (UPF/CPF basics)
🔸 Experience
Skill Requirements
Experience
15–18+ years in Design Verification
Proven track record of:
Leading chip-level DV
Multiple successful SoC tapeouts
🔸 Tools & Platforms
Simulators: VCS, Xcelium, Questa
Emulation: Palladium, Zebu (good to have)
Debug tools: Verdi, SimVision
🔸 Soft Skills
Strong debugging and analytical thinking
Ability to lead large, cross-functional teams
Clear communication with stakeholders and customers
Other Requirements
Good to Have
Experience with:
Portable Stimulus (PSS)
Formal verification exposure
Firmware-driven verification
Scripting:
Python / Perl / TCL for automation
📊 Success Metrics
Functional + code coverage closure as per targets
High bug detection efficiency pre-silicon
Minimal escapes to silicon
Regression stability and turnaround time
First-pass silicon success (functional perspective)