Job Summary

• PD-POWER (VCLP/UPF) 
• System Verilog based SoC Top RTL integration
• UPF + RTL VCLP
• Linting
• CDC/RDC checks

Key Responsibilities

1. Architect complex AMS mask layouts utilizing Cadence Virtuoso and Mentor Graphics, ensuring scalability, performance, and compliance with industry security standards.
2. Develop and optimize physical design flows for AMS circuits using advanced DRC/LVS verification tools to maintain design integrity and manufacturability.
3. Mentor team members on best practices in AMS mask design, guiding training initiatives and technical upskilling to mitigate delivery risks.
4. Lead technical reviews and solution definition by leveraging deep expertise in semiconductor process technologies and client-specific requirements.
5. Collaborate with stakeholders to gather business and technical needs, crafting technology strategies that integrate emerging EDA tools and methodologies for future-proof solutions.

Skill Requirements

1. Expert proficiency in AMS mask design using Cadence Virtuoso, Mentor Graphics, and industry-standard EDA tools.
2. Excellent understanding of semiconductor fabrication, DRC/LVS verification, and tape-out processes.
3. Advanced proficiency in physical design concepts, layout optimization, and process node migration.
4. Solid experience in developing and implementing design methodologies for complex AMS circuits.
5. Strong skills in technical leadership, training, and strategic solutioning aligned with client objectives.

Other Requirements

OP ID: 1537 --> External/Internal