Senior Technical Architect - C, Post - silicon Validation, Python
United States
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Job Description
Senior Technical Architect - C, Post - silicon Validation, Python
San Jose, California

Job Summary

Requirements: 
10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs
Hands-on ownership of PCIe or Ethernet and  some experience with UFS or LPDDR5.
Lab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue
Working knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs
Ability to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware
Scripting for lab automation and data analysis (Python preferred)
Clear written and verbal communication;

Present a margin plot and a root-cause story to design and program teams

Key Responsibilities

Requirements: 
10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs
Hands-on ownership of PCIe or Ethernet and  some experience with UFS or LPDDR5.
Lab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue
Working knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs
Ability to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware
Scripting for lab automation and data analysis (Python preferred)
Clear written and verbal communication 

Present a margin plot and a root-cause story to design and program teams

Skill Requirements

Requirements: 
10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs
Hands-on ownership of PCIe or Ethernet and  some experience with UFS or LPDDR5.
Lab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue
Working knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs
Ability to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware
Scripting for lab automation and data analysis (Python preferred)
Clear written and verbal communication

Present a margin plot and a root-cause story to design and program teams

Other Requirements

Requirements: 
10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs
Hands-on ownership of PCIe or Ethernet and  some experience with UFS or LPDDR5.
Lab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue
Working knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs
Ability to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware
Scripting for lab automation and data analysis (Python preferred)
Clear written and verbal communication

Present a margin plot and a root-cause story to design and program teams
Maximum Salary (US): 
Minimum Salary (US): 
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Information at a Glance

Why HCLTech?

At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first.

HCLTech is a global technology company, home to more than 223,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending June 2026 totaled $14.8 billion. 

 

Compensation and Benefits

A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year.