Job Summary

Role Overview

We are seeking highly motivated Memory Design Engineers with 12+ years of experience to design, develop, and optimize memory IPs (SRAM, ROM, Register files, etc.) for advanced semiconductor nodes. The role involves circuit design, characterization, and collaboration across RTL, layout, and verification teams.

Key Responsibilities

Design & Development

• Design and develop high-performance, low-power memory circuits (SRAM/ROM/Register Files).
• Work on bitcell design, peripheral circuits, sense amplifiers, decoders, and control logic.
• Drive memory architecture definition based on SoC requirements.
• Optimize designs for power, performance, and area (PPA).

Circuit Design & Analysis

• Perform transistor-level design and simulations (SPICE, Spectre, HSPICE).
• Conduct corner analysis, Monte Carlo simulations, and variation-aware design.
• Debug design issues across PVT conditions.

Integration & Collaboration

• Interface with RTL, Physical Design, DFT, and Product teams for seamless integration.
• Support layout teams for custom layout guidance and ensure DRC/LVS compliance.
• Participate in design reviews, tapeouts, and silicon validation.

Silicon Bring-up & Debug

• Analyze post-silicon results and debug failures.
• Work on yield improvement and reliability issues (aging, EM, IR drop).

Automation & Tools

• Develop scripts (Python, Perl, Shell) to automate design and verification tasks.

Skill Requirements

Technical Skills

• Strong understanding of:
• CMOS fundamentals
• Memory architectures (SRAM, ROM, emerging memory is a plus)
• Low-power design techniques
• Expertise in tools:
• Cadence Virtuoso, Spectre/HSPICE
• Layout tools & verification flows (DRC/LVS)
• Knowledge of:
• STA basics, timing closure for memory interfaces 
  Yield, variability, and reliability analysis

Other Requirements

Preferred Qualifications

• Experience with memory compilers or embedded memory IP development
• Knowledge of FinFET technologies
• Experience in high-speed interfaces or cache design

Soft Skills

• Strong problem-solving and debugging skills
• Ability to work across cross-functional teams
• Good communication and documentation skills

Education

Bachelor’s/Master’s/Ph.D. in Electronics / Electrical / VLSI / Microelectronics

• 12+ Years (Senior Level):
• Strong experience in complete memory IP design cycles from spec to silicon.
• Experience in leading modules/teams is a plus.
• Exposure to advanced nodes (≤16nm preferred).