Job Summary
| Perform end‑to‑end physical design flow: |
| Floorplanning |
| Power planning (PG grid, IR) |
| Placement & optimization |
| CTS (Clock Tree Synthesis) |
| Routing |
| Post‑route optimization |
| Achieve timing closure across all modes and corners |
| Resolve DRC, LVS, ERC and signoff violations |
| Handle low‑power design techniques: |
| Multi‑Vt, Multi‑voltage (UPF) |
| Power gating, clock gating |
| Perform physical verification and signoff: |
| STA (Primetime) |
| SI / Crosstalk |
| IR drop & EM analysis |
| Work on advanced nodes (7nm, 5nm, 3nm or below) |
| Collaborate with: |
| RTL & Micro‑architecture teams |
| DFT & Test engineers |
| Foundry and CAD teams |
| Debug complex timing, congestion, power, and variability issues |
| Drive methodology improvements and automation (scripts/flows) |
Key Responsibilities
2. Lead Training Initiatives And Knowledge Transfer Sessions To Develop Team Capabilities In Physical Design, Ensuring A High Level Of Proficiency Within The Team And Minimizing Delivery Risks.
3. Continuously Evaluate And Adopt Cutting-Edge Physical Design Technologies And Methodologies To Deliver High-Quality, Future-Proof Solutions That Meet Client Expectations And Industry Standards.
4. Utilize Domain Expertise In Physical Design To Gather And Analyze Client Requirements, Delivering Tailored Solutions And Crafting A Technology Strategy That Aligns With Overarching Business Goals.
Skill Requirements
2. Strong Understanding Of Semiconductor Design Principles And Methodologies Including Rtl To Gdsii Flow.
3. Excellent Problem-Solving Skills With The Ability To Architect Solutions For Complex Design Challenges.
4. Proficient In Scripting Languages Such As Tcl And Python For Automation In Physical Design Tasks.
Other Requirements
2. Certification In Relevant Industry Standards (E.G., Ieee, Iso) Is A Plus.