Job Summary
| E3 | Candidates with 8 to 14 years experience is mandatory |
| Experience in defining micro-architecture specifications for high-performance, low-power digital design blocks and subsystems. | |
| Experience in Full chip RTL integration | |
| Experience with ASIC/SoC development flow including synthesis/timing constraints development, Static Timing Analysis closure, resolving P& R congestion issues etc. | |
| Experience in RTL Synthesis | |
| Scripting experience | |
| Experience integrating IP's like PCIe, DDR, Ethernet etc. | |
| Should be able to lead a team of 5 to 6 leads under whom entry level engineers will be there. | |
| Expected to handle minimum 2 projects simultaneously | |
| Experience in handling and interacting with clients across different Geos. | |
| Excellent communication skills are mandatory. |
Key Responsibilities
2. Train And Mentor Team Members In Rtl Design Methodologies And Tools Such As Modelsim And Synopsys, Ensuring A Continuous Supply Of Skilled Professionals And Mitigating Delivery Risks.
3. Continuously Evaluate And Adopt Cutting-Edge Technologies And Tools, Ensuring The Delivery Of High-Quality, Future-Proof Rtl Solutions That Meet Client Expectations And Industry Standards.
4. Leverage Advanced Rtl Design Expertise To Gather Client Requirements, Provide Tailored Solutions, And Develop A Comprehensive Technology Strategy That Aligns With Business Objectives.
Skill Requirements
2. Proficiency In Vhdl, Verilog, And Systemverilog For Digital Design.
3. Strong Understanding Of Fpga And Asic Design Flows.
4. Familiarity With Simulation And Synthesis Tools Such As Modelsim, Xilinx Vivado, And Synopsys Design Compiler.
5. Excellent Problem-Solving And Analytical Skills.