Job Summary
| Candidates with 8 to 14 years experience is mandatory |
| Experience in defining micro-architecture specifications for high-performance, low-power digital design blocks and subsystems. |
| Experience in Full chip RTL integration |
| Experience with ASIC/SoC development flow including synthesis/timing constraints development, Static Timing Analysis closure, resolving P& R congestion issues etc. |
| Experience in RTL Synthesis |
| Scripting experience |
| Experience integrating IP's like PCIe, DDR, Ethernet etc. |
| Should be able to lead a team of 5 to 6 leads under whom entry level engineers will be there. |
| Expected to handle minimum 2 projects simultaneously |
| Experience in handling and interacting with clients across different Geos. |
| Excellent communication skills are mandatory. |
Key Responsibilities
2. To train and develop team so as to ensure that there is an adequate supply of trained manpower in the said technology and delivery risks are mitigated.
3. To continuously upskill with cutting-edge tech to deliver high-quality, future-proof solutions meeting client expectations and industry standards.
4. To leverage domain/tech expertise to gather client needs, deliver solutions, and craft a technology strategy aligned with business goals.