Job Summary

RTL Design Verification engineers to perform SoC leavel and block-level verification of IP components. The role involves validating functionality of IPs provided and ensuring readiness for SoC-level integration.

Key Responsibilities

• Perform RTL design verification for SoC  & IP blocks:
o FSM (Finite State Machine)
o DAC-related logic (with model interaction)
o Pattern memory / controller logic
o at the test chip top
• Test chip integration (hard ip, pads, custom logic, clock, reset etc.)
• Develop and execute comprehensive verification plans
• Build testbenches and verification environments (directed + random testing)
• Validate functional correctness and interface behaviour
• Perform debug and root cause analysis of RTL issues
• Ensure coverage closure and verification completeness
• Work closely with PD and integration teams to enable smooth SoC integration

Skill Requirements

• Strong experience in RTL Design Verification
• Write SV RTL for custom logic at the test chip top (clock, reset, FSM etc.)
• Good understanding of:
o Digital design fundamentals
o FSM-based architectures
o IP/block-level verification
o Understanding of UPF

Other Requirements

• Testbench development
• Functional verification methodologies
• Debugging and RTL issue analysis
Programming / Tools
• Working knowledge of:
o SystemVerilog / Verilog
o UVM or similar verification methodologies (preferred)
o Scripting (Python/Shell – good to have)