Senior Test Lead
United States
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Job Description
Senior Test Lead
Santa Clara, California

Job Summary

We are looking for a hands-on Electrical Engineer (EE) to perform high-speed SerDes characterization, validation, and debug for AI silicon and systems. The ideal candidate has deep experience with PCIe Gen6 and high-speed Ethernet SerDes and is comfortable operating advanced signal-integrity and SerDes characterization equipment.

Responsibilities

  • Perform SerDes electrical characterization, compliance testing, and debug.
  • Characterize PCIe Gen6 and high-speed Ethernet interfaces across voltage, temperature, and operating conditions.
  • Execute eye diagram, jitter, BER, margining, and signal-integrity measurements.
  • Debug link-training, signal-integrity, and board/channel issues.
  • Operate high-bandwidth oscilloscopes, BERTs, VNAs, protocol analyzers, and compliance test equipment.
  • Analyze characterization data and work with silicon, board, firmware, and validation teams to resolve issues.
  • Develop and automate characterization flows and data collection where applicable.

Qualifications

  • BS/MS in Electrical Engineering or equivalent experience.
  • Strong hands-on experience with high-speed SerDes characterization and debug.
  • Experience with PCIe Gen6 and high-speed Ethernet SerDes strongly preferred.
  • Strong understanding of signal integrity, jitter, eye diagrams, BER, equalization, channel loss, and link margining.
  • Hands-on experience with high-speed scopes, BERTs, VNAs, probes/fixtures, and SerDes compliance equipment.
  • Experience with board-level signal-integrity debug and silicon bring-up.
  • Experience with AI accelerators, CPUs/GPUs, server silicon, or other complex SoCs preferred.
  • Python or other scripting experience for test automation and characterization analysis is a plus.

Ideal candidate: A hands-on EE who has personally characterized and debugged PCIe Gen6/Ethernet SerDes, can independently operate high-speed characterization equipment, and can drive problems from measurement through root cause.

Key Responsibilities

We are looking for a hands-on Electrical Engineer (EE) to perform high-speed SerDes characterization, validation, and debug for AI silicon and systems. The ideal candidate has deep experience with PCIe Gen6 and high-speed Ethernet SerDes and is comfortable operating advanced signal-integrity and SerDes characterization equipment.

Responsibilities

  • Perform SerDes electrical characterization, compliance testing, and debug.
  • Characterize PCIe Gen6 and high-speed Ethernet interfaces across voltage, temperature, and operating conditions.
  • Execute eye diagram, jitter, BER, margining, and signal-integrity measurements.
  • Debug link-training, signal-integrity, and board/channel issues.
  • Operate high-bandwidth oscilloscopes, BERTs, VNAs, protocol analyzers, and compliance test equipment.
  • Analyze characterization data and work with silicon, board, firmware, and validation teams to resolve issues.
  • Develop and automate characterization flows and data collection where applicable.

Qualifications

  • BS/MS in Electrical Engineering or equivalent experience.
  • Strong hands-on experience with high-speed SerDes characterization and debug.
  • Experience with PCIe Gen6 and high-speed Ethernet SerDes strongly preferred.
  • Strong understanding of signal integrity, jitter, eye diagrams, BER, equalization, channel loss, and link margining.
  • Hands-on experience with high-speed scopes, BERTs, VNAs, probes/fixtures, and SerDes compliance equipment.
  • Experience with board-level signal-integrity debug and silicon bring-up.
  • Experience with AI accelerators, CPUs/GPUs, server silicon, or other complex SoCs preferred.
  • Python or other scripting experience for test automation and characterization analysis is a plus.

Ideal candidate: A hands-on EE who has personally characterized and debugged PCIe Gen6/Ethernet SerDes, can independently operate high-speed characterization equipment, and can drive problems from measurement through root cause.

Skill Requirements

We are looking for a hands-on Electrical Engineer (EE) to perform high-speed SerDes characterization, validation, and debug for AI silicon and systems. The ideal candidate has deep experience with PCIe Gen6 and high-speed Ethernet SerDes and is comfortable operating advanced signal-integrity and SerDes characterization equipment.

Responsibilities

  • Perform SerDes electrical characterization, compliance testing, and debug.
  • Characterize PCIe Gen6 and high-speed Ethernet interfaces across voltage, temperature, and operating conditions.
  • Execute eye diagram, jitter, BER, margining, and signal-integrity measurements.
  • Debug link-training, signal-integrity, and board/channel issues.
  • Operate high-bandwidth oscilloscopes, BERTs, VNAs, protocol analyzers, and compliance test equipment.
  • Analyze characterization data and work with silicon, board, firmware, and validation teams to resolve issues.
  • Develop and automate characterization flows and data collection where applicable.

Qualifications

  • BS/MS in Electrical Engineering or equivalent experience.
  • Strong hands-on experience with high-speed SerDes characterization and debug.
  • Experience with PCIe Gen6 and high-speed Ethernet SerDes strongly preferred.
  • Strong understanding of signal integrity, jitter, eye diagrams, BER, equalization, channel loss, and link margining.
  • Hands-on experience with high-speed scopes, BERTs, VNAs, probes/fixtures, and SerDes compliance equipment.
  • Experience with board-level signal-integrity debug and silicon bring-up.
  • Experience with AI accelerators, CPUs/GPUs, server silicon, or other complex SoCs preferred.
  • Python or other scripting experience for test automation and characterization analysis is a plus.

Ideal candidate: A hands-on EE who has personally characterized and debugged PCIe Gen6/Ethernet SerDes, can independently operate high-speed characterization equipment, and can drive problems from measurement through root cause.

Other Requirements

Ideal candidate: A hands-on EE who has personally characterized and debugged PCIe Gen6/Ethernet SerDes, can independently operate high-speed characterization equipment, and can drive problems from measurement through root cause.
Maximum Salary (US):  148000
Minimum Salary (US):  78000
Apply now
Information at a Glance

Why HCLTech?

At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first.

HCLTech is a global technology company, home to more than 223,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending June 2026 totaled $14.8 billion. 

 

Compensation and Benefits

A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year.