Job Summary

To test Verilog code as per work allocated within the quality standards prescribed so as to meet the client requirements.

Key Responsibilities

1.Develop verification plans and test strategies based on design specifications.
2.Develop testbenches using Verilog/System Verilog.
3.Perform functional and timing verification of FPGA designs 
4.Participate in design reviews to ensure testability and coverage.
5.Analyze simulation results and debug failures using waveform analysis tools.
6.Collaborate with design engineers to resolve defects and improve RTL quality.
7.Experience with FPGA simulation platforms
8.Familiarity with interfaces such as SPI & UART
9.Basic scripting knowledge: Python / TCL
10.Document test results and reports

Skill Requirements

1. Develop the test environment from scratch
2. Handson verification tool
3. Test bench creation for AHDL code

Other Requirements