Job Summary

Define ASIC/SoC verification strategy Good understanding of ASIC/SoC life cycle Full chip testplan development Has participated in multiple ASIC/SoC verification till  tapeout stage Full chip TB Architecture definition Experience writing ASIC/SoC testplans UVM based testbench development 1.Experience in ASIC/SoC Testbench definition 2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM). SV functional coverage, Assertions coding 1.Expertise & hands-on experience in OVM/UVM methodologies using SV 2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans. C based TB development 1. Experience in developing TB compone EducationDegree: Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), VLSI Design, or a closely related field Core Technical Skills Proven industry experience in ASIC/SoC design and verification with multiple successful tape-outs. Expert Languages: Mastery of SystemVerilog, Verilog, and UVM (Universal Verification Methodology). Digital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.  Processor Knowledge: Strong understanding of CPU/GPU architectures, cache coherency, and memory controllers (e.g., DDR4/DDR5, HBM) is highly desirable. Tools: Expert proficiency with industry-leading EDA simulators, debuggers (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verd), and emulation platforms.  Protocols: Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE). Scripting: Advanced capability in Python, Tcl, or Perl to create custom automation infrastructure for regressions and metrics tracking. Soft Skills Strategic Thinking: Ability to foresee technical risks weeks or months in advance and proactively implement mitigation strategies. Influence: Strong leadership and communication skills to guide cross-functional teams and align

Key Responsibilities

1. To assess the domain IT landscape assessment and Application portfolio optimization for gap analysis
2. Creation of solution and architectural views (logical| conceptual| development| execution| infrastructure & operations architecture)
3. To study and define system requirements addressing stakeholder| portfolio concerns
4. To ensure knowledge up-gradation and work with new and emerging products/technologies
5. To manage Non Functional Requirement adaption for the solution
6. To contribute towards white/technical papers and knowledge base

Skill Requirements

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Other Requirements

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