Job Summary
The IP Interface Manager will serve as the primary interface between HCLTech's semiconductor engineering teams and external IP suppliers, including semiconductor IP vendors, EDA partners, foundries, and technology ecosystem partners.
The role is responsible for coordinating IP selection, technical evaluation, licensing, integration readiness, documentation, issue resolution, and delivery commitments across ASIC and SoC development programs. The individual will ensure that third-party IP meets project requirements, design specifications, foundry-process compatibility, and program schedules.
Key Responsibilities
A. IP Vendor Interface and Coordination
- Act as the primary operational interface for third-party semiconductor IP vendors.
- Coordinate with IP suppliers covering Arm processor IP, RISC-V IP, interface IP, memory IP, analog/mixed-signal IP, security IP, and high-speed connectivity IP.
- Manage technical discussions, vendor queries, issue tracking, and action-item closure.
- Coordinate with IP vendors on product roadmaps, IP availability, technology transitions, and support commitments.
- Maintain effective working relationships with EDA, foundry, and ecosystem partners.
B. IP Evaluation and Integration Readiness
- Coordinate IP evaluation against SoC architecture, performance, power, area, process-node, and interface requirements.
- Collect and review IP deliverables, including RTL, integration guides, timing constraints, verification collateral, testbenches, and implementation guidelines, as applicable.
- Track IP qualification, silicon-proven status, process-porting requirements, and design-rule compatibility.
- Coordinate IP integration dependencies with architecture, RTL, verification, physical design, DFT, firmware, and product engineering teams.
- Facilitate resolution of integration issues and escalate technical risks to the responsible engineering owners.
C. IP Licensing and Commercial Coordination
- Coordinate with procurement, legal, finance, and business teams on IP licensing requirements, NDAs, evaluation agreements, and contractual deliverables.
- Track licensing scope, usage rights, project entitlements, deliverable schedules, support obligations, and renewal requirements.
- Maintain an IP register covering vendor, IP category, technology node, license status, delivery status, and project usage.
- Support IP cost estimation and commercial comparisons in coordination with procurement and program management.
D. Program and Delivery Management
- Track IP procurement and delivery milestones against the overall SoC development schedule.
- Maintain an IP readiness dashboard, risk register, dependency matrix, and issue log.
- Coordinate vendor support during design integration, verification, tapeout, and post-silicon debugging.
- Identify risks associated with late IP delivery, incomplete collateral, unsupported process nodes, and vendor resource constraints.
- Drive timely escalation and closure of open actions across internal teams and external suppliers.
E. Cross-Functional Collaboration
- Work closely with SoC architects, design leads, verification teams, physical design engineers, DFT teams, and program managers.
- Coordinate with foundry and IP ecosystem partners to confirm process-specific IP availability and readiness.
- Support customer technical reviews, IP status reporting, and project governance meetings.
- Capture lessons learned and improve IP sourcing, qualification, integration, and vendor-management processes.
Skill Requirements
3. Required Qualifications
- Bachelor's or master's degree in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related field.
-14+ years of experience in semiconductor engineering, ASIC/SoC development, IP integration, IP vendor management, or semiconductor program coordination.
- Working knowledge of semiconductor IP categories, SoC development flows, and IP integration dependencies.
- Experience coordinating with external semiconductor vendors and cross-functional engineering teams.
- Understanding of semiconductor IP licensing, deliverables, engineering schedules, and issue-management processes.
4. Preferred Technical Knowledge
- Arm and/or RISC-V processor IP.
- AMBA AXI/AHB/APB, PCIe, USB, Ethernet, MIPI, LPDDR/DDR, UCIe, and other standard IP interfaces.
- SRAM/ROM, PLL, clocking, analog/mixed-signal, security, and peripheral IP.
- Foundry-specific IP availability and process-node compatibility.
- EDA tools, IP verification collateral, timing constraints, integration documentation, and design sign-off concepts