Job Summary
Key Responsibilities
2. Oversee the verification and sign-off of mask layouts through DRC/LVS tools, maintaining compliance with foundry and regulatory standards.
3. Define and enforce best practices in AMS mask design methodologies, including hierarchical layout planning and parasitic extraction, to optimize performance and yield.
4. Provide architectural guidance for integrating analog, RF, and mixed-signal components within SOC projects, leveraging advanced EDA tools for solution delivery.
5. Collaborate with cross-functional engineering teams to align AMS mask design deliverables with overall silicon design and tape-out schedules.
6. Drive process improvement initiatives by evaluating emerging EDA technologies and recommending adoption strategies for increased efficiency and innovation.
Skill Requirements
2. Excellent understanding of process design kits (PDK), layout versus schematic (LVS), and design rule checks (DRC).
3. Advanced proficiency in analog, RF, and mixed-signal layout methodologies, including hierarchical planning and parasitic extraction.
4. Solid expertise in silicon integration, tape-out processes, and cross-domain collaboration within semiconductor environments.
5. Strategic technical direction capabilities, with a strong focus on innovation and continuous process improvement.
Other Requirements
2. Optional but valuable: Mentor Graphics Certified Layout Engineer