Job Summary
| Candidates with 8 to 14 years experience is mandatory |
| Experience in defining micro-architecture specifications for high-performance, low-power digital design blocks and subsystems. |
| Experience in Full chip RTL integration |
| Experience with ASIC/SoC development flow including synthesis/timing constraints development, Static Timing Analysis closure, resolving P& R congestion issues etc. |
| Experience in RTL Synthesis |
| Scripting experience |
| Experience integrating IP's like PCIe, DDR, Ethernet etc. |
| Should be able to lead a team of 5 to 6 leads under whom entry level engineers will be there. |
| Expected to handle minimum 2 projects simultaneously |
| Experience in handling and interacting with clients across different Geos. |
| Excellent communication skills are mandatory. |
Key Responsibilities
2. Lead And Mentor The Development Team In Rtl Design Methodologies And Tools, Fostering Skill Enhancement To Ensure A Robust Pipeline Of Expertise And Mitigate Delivery Risks.
3. Research And Incorporate State-Of-The-Art Rtl Design Technologies, Ensuring Solutions Remain Current And Meet Rigorous Quality Standards And Client Expectations.
4. Collaborate With Stakeholders To Gather Specifications, Translating Business Requirements Into Effective Rtl Design Solutions That Meet Organizational Goals.
Skill Requirements
2. Strong Understanding Of Digital Design Principles And Methodologies.
3. Familiarity With Fpga And Asic Design Flows.
4. Excellent Problem-Solving And Analytical Skills.
5. Proficient In Using Simulation Tools And Verification Methodologies.