Job Summary

FPGA RTL Design & Validation E3.1

Candidates with 5 to 10 years’ experience is mandatory

Experience in defining micro-architecture specifications for high-performance, low-power digital design blocks and subsystems.

Key Responsibilities

Experience in Full chip RTL integration

Experience with ASIC/SoC development flow including synthesis/timing constraints development, Static Timing Analysis closure, resolving P& R congestion issues etc.

Experience in RTL Synthesis

Skill Requirements

Scripting experience

Experience integrating IP's like PCIe, DDR, Ethernet etc.

Should be able to lead a team of 5 to 6 leads under whom entry level engineers will be there.

Other Requirements

Expected to handle minimum 2 projects simultaneously

Experience in handling and interacting with clients across different Geos.

Excellent communication skills are mandatory.