Job Summary

We are seeking an expert Full-Chip TFM CAD Physical Design Engineer to own, architect, and optimize our digital implementation and sign-off flow environments. In this role, you will design robust, enterprise-grade automated pipelines that control the full layout lifecycle—from hierarchical floorplanning and logic synthesis to clock tree synthesis, routing, timing closure, and tape-out sign-off. You will collaborate closely with physical design execution leads, infrastructure/HPC teams, and leading EDA vendors to drive Best-in-Class Power, Performance, and Area (PPA) and design productivity across advanced foundry process nodes.

Key Responsibilities

• Define, build, and deploy the automated hierarchical RTL-to-GDSII execution flows used across all block-level and full-chip integration platforms
• Evaluate and introduce next-generation EDA features, including AI-driven optimization engines, advanced routing techniques, and hierarchical physical synthesis.
• Standardize database hand-offs, data structures, and revision controls between IPs, subsystems, and the top-level full-chip environment.
• Set up, calibrate, and automate critical full-chip sign-off tracks, including Static Timing Analysis (STA), Electromigration & IR Drop (EMIR), Low-Power verification (UPF), and Design Rule Checking (DRC/LVS)
• Scale the CAD environment to support massive, multi-billion transistor designs. Drive regressions using distributed grid computing (HPC) with high memory-to-runtime efficiency
• Serve as the technical point of contact for foundry PDK (Process Design Kit) updates and EDA vendor tracking. Resolve tool-level regressions and tool anomalies
• Develop in-house verification scripts, layout audit dashboards, and zero-tolerance "sanity checkers" to catch floorplanning or power-grid setup bugs early.

Skill Requirements

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Science (with a VLSI focus)
• Strong foundational expertise in TFM infrastructure development or advanced digital implementation layout pipelines.
• Expert proficiency inside either the Synopsys environment (Fusion Compiler, IC Compiler II, PrimeTime, VC LP, StarRC) or the Cadence suite (Innovus, Tempus, Voltus, Pegasus).
• High-level mastery of TCL (specifically tool data models like dbGet or Synopsys application interfaces) and Python/Perl for big data text parsing. Experience with Unix shell environments and Git/Perforce version control is required.
• Working knowledge of layout limitations and design rule check (DRC) complexities at sub-5nm nodes (e.g., cell architecture, multi-patterning, spike resistance).
• Deep understanding of physical design execution, including clock tree synthesis (CTS), multi-voltage low-power (UPF/CPF) structures, and chip-package interface definitions
• Experience deploying containerized workflows (Docker/Singularity) or distributed batch job management setups (LSF, Slurm)

Other Requirements

A Full-Chip TFM (Tools, Flows, and Methodologies) CAD Physical Design Engineer is a highly technical professional who bridges the gap between EDA tool vendors, technology foundries, and the physical design team. Rather than executing block-level designs manually, this role focuses on architecting, automating, and scaling the entire full-chip digital implementation pipeline (RTL-to-GDSII).

At the full-chip level, this role guarantees that massive SoC databases can smoothly pass through layout, timing, low-power compliance, and manufacturing reliability checks with optimal compute scalability and predictable runtime