Job Summary
We are seeking a Principal / Staff Physical Verification Engineer with 10+ years of experience to drive the full-chip layout verification strategy and manufacturing sign-off for our next-generation, high-performance SoCs. In this critical technical leadership role, you will own the end-to-end execution of Design Rule Checking (DRC), Layout Versus Schematic (LVS), Electrical Rule Checking (ERC), and Design for Manufacturing (DFM) pipelines at the full-chip level. You will act as the ultimate technical authority bridging physical design implementation (PnR), analog/mixed-signal IP integration, and external silicon foundries to guarantee 100% hazard-free, high-yielding silicon on advanced process nodes.
Key Responsibilities
- Lead the definition, deployment, and execution of full-chip hierarchical physical verification methodologies (DRC, LVS, ERC, ESD, Antenna, and DFM).
- Serve as the primary technical interface with leading silicon foundries (e.g., TSMC, Intel, Samsung). Critically evaluate, customize, and deploy foundry Process Design Kits (PDKs) and verification runset
- Architect clean database aggregation models. Standardize layout hand-offs between third-party IPs, mixed-signal blocks, digital subsystems, and the top-level full-chip environment
- Troubleshoot, root-cause, and debug the most complex full-chip structural violations—such as massive LVS text-shorts, complex soft-check loops, deep sub-micron multi-patterning (EUV) coloring errors, and latch-up issues
- Establish and enforce strict corporate-wide physical verification waiver policies. Conduct formal layout sign-off reviews and audit block-level violations to minimize masked silicon risks
- Scale the physical verification workspace to support multi-billion transistor designs. Drive execution efficiency by optimizing tool runtime, memory footprint, and multi-threading allocation across massive High-Performance Computing (HPC) grid environments
Author internal layout checklists and mandatory sign-off criteria for corporate tape-outs. Mentor, guide, and perform quality reviews for mid-level and junior layout engineers
Skill Requirements
- Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or related field.
- 10+ years of direct physical verification experience, with a definitive track record of closing and signing off complex, multi-million instance full-chip SoC tape-outs.
- Expert-level, command-line mastery of industry-standard sign-off tools, specifically Siemens Calibre (Calibre nmDRC, nmLVS, PERC) or Synopsys IC Validator (ICV), or Cadence Pegasus
- Proven experience closing physical design rules on sub-5nm FinFET or GAA process geometries (e.g., N5, N3, N2), including deep exposure to complex multi-patterning, dummy metal fill requirements, and stress effects.
- Advanced proficiency in parsing, modifying, and custom-coding verification decks using Standard Verification Rule Format (SVRF/TVF) or tool-equivalent runset languages.
- High proficiency in TCL, Python, or Perl to build custom error parsers, automated layout verification tracking dashboards, and continuous integration regressions.
Other Requirements
An Architect / Principal Physical Verification Engineer with 10+ years of experience is a subject matter expert who owns the ultimate structural layout integrity, manufactureability, and foundry sign-off for a System-on-Chip (SoC). At this senior level, the role shifts from running individual tool decks to architecting full-chip hierarchical verification methodologies, establishing waiver policies, resolving complex manufacturing anomalies, and directly interface-managing foundry partnerships to secure maximum yield before tape-out.