Job Summary

We are seeking a highly collaborative and structured Technical Program Manager (TPM) for Physical Design to drive the execution, scheduling, and delivery of our next-generation, high-performance SoCs. In this role, you will be the core driver keeping the RTL-to-GDSII physical implementation timeline on track. You will combine your technical VLSI background with program management methodologies to manage cross-functional dependencies, identify bottlenecks, mitigate tape-out risks, and communicate milestone health to executive leadership.

Key Responsibilities

• Define, build, and execute the end-to-end program plan for full-chip physical implementation, spanning early synthesis, floorplanning, PnR, CTS, timing closure, sign-off, and final GDSII delivery.
• Coordinate and track critical dependencies across upstream and downstream teams, including RTL Front-End, Design Verification (DV), DFT, Package Design, Signal/Power Integrity, and Foundry partners.
• Proactively identify technical, resource, or schedule bottlenecks (e.g., late RTL drops, timing closure stalls, EMIR or DRC hotspots). Drive engineering teams to build concrete recovery plans.
• Orchestrate milestone reviews (e.g., Netlist Ready, Floorplan Freeze, Tape-out Sign-off Reviews) to ensure all entry and exit criteria are rigorously met.
• Translate highly complex technical layouts, layout bugs, and timing closure metrics into clear, high-level status dashboards and execution updates for executive stakeholders.
• Continuously evaluate and refine the physical design execution flow. Implement agile tracking systems, retrospective frameworks, and automation hooks to accelerate future tape-out cycles.

Skill Requirements

• 10+ years of total experience in the semiconductor industry, with a minimum of 3+ years acting as a TPM or Engineering Lead specifically handling digital physical design.
• Strong working knowledge of the digital implementation flow (Synthesis, PnR, CTS, STA/Timing Closure, Physical Verification, and EMIR). You must be able to understand technical discussions with engineers and question resource limitations.
• Expert proficiency in program tracking suites such as Jira, Confluence, Microsoft Project, Smartsheet, or equivalent Agile/Waterfall frameworks.

Other Requirements

• PMP (Project Management Professional) or Agile/Scrum certification is a plus, provided it is backed by deep VLSI engineering experience.
• Outstanding interpersonal and conflict-resolution skills, with a proven ability to influence engineering teams across multiple geographic sites without direct authority.
• Experience managing high-pressure environments during final tape-out crunch phases.