Job Summary

This role is responsible for driving the architectural vision and technical leadership for advanced memory characterization solutions. The individual leverages deep expertise to design enterprise-scale, high-performance frameworks and methodologies in alignment with emerging industry standards and technology trends. The position ensures that solutions are scalable, robust, and strategically aligned with client objectives, while fostering innovation and technical excellence across teams.

Key Responsibilities

1. Architect and design comprehensive memory characterization solutions using advanced methodologies and industry-leading tools such as Cadence, Synopsys, and Mentor Graphics, ensuring scalability and alignment with project goals.
2. Lead the development and implementation of memory characterization workflows, integrating latest protocols and automation techniques to enhance accuracy and throughput.
3. Define and enforce architectural governance, compliance, and best practices for memory characterization, utilizing deep domain knowledge to guide technical standards and quality benchmarks.
4. Collaborate with internal teams to translate client requirements into innovative, technically sound memory characterization strategies, driving adoption of new technologies and approaches.
5. Mentor and train team members on advanced memory characterization techniques, tools, and emerging trends to build technical capability and mitigate delivery risks.
6. Author technical whitepapers, contribute to industry forums, and initiate patent filings to establish organizational leadership and drive thought leadership in the memory characterization domain.

Skill Requirements

1. Architectural Leadership in memory characterization with expert proficiency in Cadence, Synopsys, and Mentor Graphics.
2. Advanced knowledge of device physics, memory protocols (DRAM, SRAM, Flash), and automated test environments.
3. Excellent understanding of characterization algorithms, performance modeling, and statistical data analysis.
4. Expertise in developing and enforcing technical governance and quality standards in semiconductor memory projects.
5. Strong skills in technical mentoring, process optimization, and driving innovation across teams.

Other Requirements

1. Recommended: Certified LabVIEW Architect (CLA), Synopsys Certified Professional, Cadence Certified Architect (optional but valuable).
2. Recommended: Participation in IEEE or JEDEC memory standards working groups (optional but valuable).