Technical Specialist - Silicon Platform Validation, Python
United States
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Job Description
Technical Specialist - Silicon Platform Validation, Python
Santa Clara, California

Job Summary

We are looking for a Silicon Interposer Design Engineer to drive the physical design, layout, and
technology development of silicon interposers used in next-generation 2.5D and 3D
heterogeneous integration platforms. You will own the interposer design from architecture
definition through tapeout, working at the intersection of semiconductor process technology,
package integration, and system-level performance optimization.

Key Responsibilities

Lead the physical design and layout of silicon interposers for multi-chiplet integration
(compute, HBM, I/O, networking dies)
● Define interposer architecture including die placement, bump map assignment, RDL
routing strategy, TSV farm layout, and power/ground distribution
● Develop and optimize RDL (Redistribution Layer) routing for high-density die-to-die
interconnects, ensuring compliance with electrical, thermal, and mechanical constraints
● Design TSV (Through-Silicon Via) arrays and transitions — including TSV placement,
keep-out zones, stress-aware floorplanning, and landing pad optimization
● Collaborate with SI/PI engineers to meet signal integrity and power delivery targets
across the interposer
● Define and validate interposer stackup (metal layers, dielectric thickness, TSV
dimensions) in coordination with foundry process capabilities
● Perform DRC/LVS verification and ensure design compliance with foundry design rules
(TSMC CoWoS, UMC, GlobalFoundries, etc.)
● Work with EDA tool flows for interposer-specific design (custom routing, via pillar arrays,
micro-bump pitch optimization)
● Co-optimize interposer design with package substrate and PCB teams for seamless
chip-package-board integration
● Support thermal-mechanical analysis by providing accurate layout data for warpage,
stress, and reliability simulations
● Interface with foundry partners for technology selection, design rule clarification, and
tapeout execution
● Drive DFM/DFT strategies to improve yield and testability of interposer-based products
● Support silicon bring-up, debug, and failure analysis of interposer-related issues

Skill Requirements

5+ years of experience in silicon interposer design, advanced packaging physical
design, or semiconductor back-end-of-line (BEOL) design
● Strong proficiency with physical design and layout tools:
○ Layout & Routing: Cadence Virtuoso, Cadence APD (Advanced Package
Designer), Synopsys IC Compiler II, Siemens Calibre
○ Verification: Cadence PVS, Mentor Calibre (DRC/LVS/ERC)
○ Parasitic Extraction: StarRC, QRC, Calibre xRC
● Deep understanding of silicon interposer process technology:
○ RDL metallization (Cu damascene, semi-additive process)
○ TSV fabrication (via-first, via-middle, via-last)
○ Micro-bump and C4 bump technology
○ Wafer thinning and backside processing
● Experience with high-density routing at fine pitch (< 1 µm L/S for RDL, < 10 µm TSV
pitch)
● Knowledge of design-for-reliability (DFR): electromigration, stress migration, thermal
cycling, and Cu pumping in TSVs
● Familiarity with foundry PDKs and process design kits for interposer technologies
● Scripting skills (Python, Tcl, SKILL) for design automation and custom DRC rule
developmen

Technical Environment
Domain Tools & Technologies
Physical Design & Layout Cadence Virtuoso, APD, Allegro SiP, Synopsys IC Compiler II
Verification (DRC/LVS) Cadence PVS, Siemens Calibre, IC Validator
Parasitic Extraction StarRC, QRC, Calibre xRC
EM/Electrical Analysis Ansys HFSS, Cadence Clarity, Sigrity
Thermo-Mechanical Ansys Mechanical, Ansys Icepak, COMSOL Multiphysics
Scripting & Automation Python, Tcl, Cadence SKILL, Perl
Foundry Platforms TSMC CoWoS (S/R/L), UMC, GlobalFoundries, Samsung I-Cube
Interconnect Standards UCIe, HBM3/3E PHY, PCIe Gen5/6, high-speed SerDes

Other Requirements

TSV Design: Via-middle Cu TSV (5–10 µm diameter), high-aspect-ratio TSV arrays,
annular keep-out zone management, TSV-induced stress modeling
● RDL Routing: Ultra-fine-pitch Cu RDL (0.4–2 µm L/S), multi-layer redistribution (4–6
RDL layers), impedance-controlled differential routing
● Bump Technology: Micro-bumps (< 40 µm pitch), Cu pillar + solder cap, hybrid bonding
pads (< 10 µm pitch)
● Interposer Stackup: Si substrate (100–150 µm thinned), multi-layer Cu/SiO₂ BEOL,
passivation and UBM layers
● Integration Platforms: 2.5D side-by-side, 3D face-to-face stacking, bridge die
(EMIB-style), fan-out on substrat
Maximum Salary (US):  172000
Minimum Salary (US):  87000
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Information at a Glance

Why HCLTech?

At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first.

HCLTech is a global technology company, home to more than 227,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending March 2026 totaled $14.7 billion. 

 

Compensation and Benefits

A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year.